Datasheet

Rev. I|Page 54 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
Capacitive Loading
Output delays and holds are based on standard capacitive loads:
30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on
Page 56 show how output rise time varies with capacitance. The
delay and hold specifications given should be derated by a factor
derived from these figures. The graphs in these figures may not
be linear outside the ranges shown.
Figure 50. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
T1
ZO = 50Ω (impedance)
TD = 4.04 ± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50Ω
0.5pF
70Ω
400Ω
45Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50Ω
Figure 51. Typical Output Delay or Hold for Driver A at V
DDEXT
Min
Figure 52. Typical Output Delay or Hold for Driver A at V
DDEXT
Max
LOAD CAPACITANCE (pF)
RISE TIME
RISE AND FALL TIME ns (10%to 90%)
14
12
10
8
6
4
2
0
0 50 100 150 200 250
FALL TIME
LOAD CAPACITANCE (pF)
RISE TIME
RISE AND FALL TIME ns (10% to 90%)
12
10
8
6
4
2
0
0 50 100 150 200 250
FALL TIME