Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 53 of 68 | July 2010
TEST CONDITIONS
All timing parameters appearing in this data sheet were
measured under the conditions described in this section.
Figure 48 shows the measurement point for ac measurements
(other than output enable/disable). The measurement point is
V
MEAS
= V
DDEXT
/2.
Output Enable Time
Output pins are considered to be enabled when they have made
a transition from a high impedance state to the point when they
start driving. The output enable time t
ENA
is the interval from
the point when a reference signal reaches a high or low voltage
level to the point when the output starts driving as shown in the
Output Enable/Disable diagram (Figure 49). The time
t
ENA_MEASURED
is the interval from when the reference signal
switches to when the output voltage reaches 2.0 V (output high)
or 1.0 V (output low). Time t
TRIP
is the interval from when the
output starts driving to when the output reaches the 1.0 V or
2.0 V trip voltage. Time t
ENA
is calculated as shown in
the equation:
If multiple pins (such as the data bus) are enabled, the measure-
ment value is that of the first pin to start driving.
Output Disable Time
Output pins are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The time for the voltage on the bus
to decay by ΔV is dependent on the capacitive load, C
L
, and the
load current, I
L
. This decay time can be approximated by
the equation:
The output disable time t
DIS
is the difference between
t
DIS_MEASURED
and t
DECAY
as shown in Figure 49. The time
t
DIS_MEASURED
is the interval from when the reference signal
switches to when the output voltage decays ΔV from the mea-
sured output-high or output-low voltage. The time t
DECAY
is
calculated with the test loads C
L
and I
L
, and with ΔV
equal to 0.5 V.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose ΔV
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. A
typical ΔV is 0.4 V. C
L
is the total bus capacitance (per data line),
and I
L
is the total leakage or three-state current (per data line).
The hold time is t
DECAY
plus the minimum disable time (for
example, t
DSDAT
for an SDRAM write cycle).
Figure 48. Voltage Reference Levels for AC Measurements (Except
Output Enable/Disable)
INPUT
OR
OUTPUT
V
MEAS
V
MEAS
t
ENA
t
ENA_MEASURED
t
TRIP
–=
Figure 49. Output Enable/Disable
t
DECAY
C
L
VΔ()I
L
⁄=
REFERENCE
SIGNAL
t
DIS
OUTPUT STARTS DRIVING
V
OH
(MEASURED)  V
V
OL
(MEASURED) + V
t
DIS_MEASURED
V
OH
(MEASURED)
V
OL
(MEASURED)
V
TRIP
(HIGH)
V
OH
(MEASURED
)
V
OL
(MEASURED)
HIGH IMPEDANCE STATE
OUTPUT STOPS DRIVING
t
ENA
t
DECAY
t
ENA_MEASURED
t
TRIP
V
TRIP
(LOW)