Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 49 of 68 | July 2010
Table 44. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter
1, 2
MinMaxUnit
t
ECOLH
COL Pulse Width High t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
ns
t
ECOLL
COL Pulse Width Low t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
ns
t
ECRSH
CRS Pulse Width High t
ETxCLK
× 1.5 ns
t
ECRSL
CRS Pulse Width Low t
ETxCLK
× 1.5 ns
1
MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to both
the ETxCLK and the ERxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Table 45. 10/100 Ethernet MAC Controller Timing: MII Station Management
Parameter
1
MinMaxUnit
t
MDIOS
MDIO Input Valid to MDC Rising Edge (Setup)10ns
t
MDCIH
MDC Rising Edge to MDIO Input Invalid (Hold)10ns
t
MDCOV
MDC Falling Edge to MDIO Output Valid 25 ns
t
MDCOH
MDC Falling Edge to MDIO Output Invalid (Hold)–1ns
1
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
Figure 30. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Figure 31. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
t
ERXCLKIS
t
ERXCLKIH
ERxD3–0
ERxDV
ERxER
ERx_CLK
t
ERXCLKW
t
ERXCLK
t
ETXCLKOH
ETxD3–0
ETxEN
MIITxCLK
t
ETXCLK
t
ETXCLKOV
t
ETXCLKW