Datasheet

Rev. I|Page 48 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
10/100 Ethernet MAC Controller Timing
Table 40 through Table 45 and Figure 30 through Figure 35
describe the 10/100 Ethernet MAC controller operations. This
feature is only available on the ADSP-BF536 and ADSP-BF537
processors.
Table 40. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter
1
MinMaxUnit
f
ERXCLK
ERxCLK Frequency (f
SCLK
= SCLK Frequency)None 25 + 1%
f
SCLK
+ 1%
MHz
t
ERXCLKW
ERxCLK Width (t
ERxCLK
= ERxCLK Period) t
ERxCLK
× 35% t
ERxCLK
× 65% ns
t
ERXCLKIS
Rx Input Valid to ERxCLK Rising Edge (Data In Setup)7.5 ns
t
ERXCLKIH
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold)7.5 ns
1
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Table 41. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter
1
MinMaxUnit
f
ETXCLK
ETxCLK Frequency (f
SCLK
= SCLK Frequency )None 25 + 1%
f
SCLK
+ 1%
MHz
t
ETXCLKW
ETxCLK Width (t
ETXCLK
= ETxCLK Period) t
ETxCLK
× 35% t
ETxCLK
× 65% ns
t
ETXCLKOV
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid)20ns
t
ETXCLKOH
ETxCLK Rising Edge to Tx Output Invalid (Data Out Hold)0 ns
1
MII outputs synchronous to ETxCLK are ETxD3–0.
Table 42. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter
1
MinMaxUnit
f
REFCLK
REF_CLK Frequency (f
SCLK
= SCLK Frequency)None 50 + 1%
2 × f
SCLK
+ 1%
MHz
t
REFCLKW
REF_CLK Width (t
REFCLK
= REFCLK Period) t
REFCLK
× 35% t
REFCLK
× 65% ns
t
REFCLKIS
Rx Input Valid to RMII REF_CLK Rising Edge (Data In Setup)4 ns
t
REFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In Hold)2 ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Table 43. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
Parameter
1
MinMaxUnit
t
REFCLKOV
RMII REF_CLK Rising Edge to Tx Output Valid (Data Out Valid)7.5 ns
t
REFCLKOH
RMII REF_CLK Rising Edge to Tx Output Invalid (Data Out Hold)2 ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.