Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 47 of 68 | July 2010
JTAG Test and Emulation Port Timing
Table 39 and Figure 29 describe JTAG port operations.
Table 39. JTAG Port Timing
Parameter MinMaxUnit
Timing Parameters
t
TCK
TCK Period 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
4 ns
t
HSYS
System Inputs Hold After TCK High
1
5 ns
t
TRSTW
TRST Pulse Width
2
(Measured in TCK Cycles)4TCK
Switching Characteristics
t
DTDO
TDO Delay From TCK Low 10 ns
t
DSYS
System Outputs Delay After TCK Low
3
012ns
1
System Inputs = DATA15–0, BR, ARDY, SCL, SDA, TFS0, TSCLK0, RSCLK0, RFS0, DR0PRI, DR0SEC, PF15–0, PG15–0, PH15–0, MDIO, TCK, TRST, RESET, NMI, RTXI,
BMODE2–0.
2
50 MHz maximum
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, BG, BGH, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, MDC, MDIO,
TSCLK0, TFS0, RFS0, RSCLK0, DT0PRI, DT0SEC, PF15–0, PG15–0, PH15–0, RTXO, TDO, EMU, XTAL, VROUT1–0.
Figure 29. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS