Datasheet

Rev. I|Page 46 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
Timer Clock Timing
Table 37 and Figure 27 describe timer clock timing.
Timer Cycle Timing
Table 38 and Figure 28 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Table 37. Timer Clock Timing
Parameter MinMaxUnit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High 12 ns
Figure 27. Timer Clock Timing
PPI_CLK
TMRx OUTPUT
t
TODP
Table 38. Timer Cycle Timing
2.25 V ≤ V
DDEXT
< 2.70 V
or
0.80 V ≤ V
DDINT
< 0.95 V
1
2.70 V ≤ V
DDEXT
≤ 3.60 V
and
0.95 V ≤ V
DDINT
≤ 1.43 V
2, 3
Parameter MinMaxMinMaxUnit
Timing Characteristics
t
WL
Timer Pulse Width Input Low (Measured In SC LK Cycles)
4
1 × t
SCLK
1 × t
SCLK
ns
t
WH
Timer Pulse Width Input High (Measured In SCLK Cycles)
4
1 × t
SCLK
1 × t
SCLK
ns
t
TIS
Timer Input Setup Time Before CLKOUT Low
5
5.55.0 ns
t
TIH
Timer Input Hold Time After C LKOUT Low
5
1.51.5 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output (Measured In SCLK Cycles)1 × t
SCLK
(2
32
–1) × t
SCLK
1 × t
SCLK
(2
32
–1) × t
SCLK
ns
t
TOD
Timer Output Update Delay After CLKOUT High 6.56.0 ns
1
Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2
Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3
All automotive-grade devices are within these specifications.
4
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
5
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 28. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO