Datasheet

Rev. I|Page 44 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
Serial Peripheral Interface Port—Slave Timing
Table 35 and Figure 25 describe SPI port slave operations.
Table 35. Serial Peripheral Interface (SPI) Port—Slave Timing
Parameter MinMaxUnit
Timing Requirements
t
SPICHS
Serial Clock High Period 2 × t
SCLK
–1.5 ns
t
SPICLS
Serial Clock Low Period 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
ns
t
HDS
Last SCK Edge to SPISS Not Asserted 2 × t
SCLK
–1.5 ns
t
SPITDS
Sequential Trans fer Delay 2 × t
SCLK
–1.5 ns
t
SDSCI
SPISS Assertion to First SCK Edge 2 × t
SCLK
–1.5 ns
t
SSPID
Data Input Valid to SCK Edge (Data Input Setup)1.6 ns
t
HSPID
SCK Sampling Edge to Data Input Invalid 1.6 ns
Switching Characteristics
t
DSOE
SPISS Assertion to Data Out Active 08ns
t
DSDHI
SPISS Deassert ion to Data High Impedance 08ns
t
DDSPID
SCK Edge to Data Out Valid (Data Out Delay)10ns
t
HDSPID
SCK Edge to Data Out Invalid (Data Out Hold)0ns
Figure 25. Serial Peripheral Interface (SPI) Port—Slave Timing
t
SPICLK
t
HDS
t
SPITDS
t
SDSCI
t
SPICLS
t
SPICHS
t
DSOE
t
DDSPID
t
DDSPID
t
DSDHI
t
HDSPID
t
SSPID
t
DSDHI
t
HDSPID
t
DSOE
t
HSPID
t
SSPID
t
DDSPID
SPIxSS
(INPUT)
SPIxSCK
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
SPIxMISO
(OUTPUT)
SPIxMOSI
(INPUT)
CPHA = 1
CPHA = 0
t
HSPID