Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 43 of 68 | July 2010
Serial Peripheral Interface Port—Master Timing
Table 34 and Figure 24 describe SPI port master operations.
Table 34. Serial Peripheral Interface (SPI) Port—Master Timing
2.25 V ≤ V
DDEXT
< 2.70 V
or
0.80 V ≤ V
DDINT
< 0.95 V
1
2.70 V ≤ V
DDEXT
≤ 3.60 V
and
0.95 V ≤ V
DDINT
≤ 1.43 V
2, 3
Parameter MinMaxMinMaxUnit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data Input Setup)8.77.5 ns
t
HSPIDM
SCK Sampling Edge to Data Input Invalid –1.5–1.5 ns
Switching Characteristics
t
SDSCIM
SPISELx Low to First SCK Edge 2 × t
SCLK
–1.52 × t
SCLK
–1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
–1.52 × t
SCLK
–1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
–1.52 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
–1.54 × t
SCLK
–1.5 ns
t
HDSM
Last SCK Edge to SPISELx High 2 × t
SCLK
–1.52 × t
SCLK
–1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
–1.52 × t
SCLK
–1.5 ns
t
DDSPIDM
SCK Edge to Data Out Valid (Data Out Delay)6 6ns
t
HDSPIDM
SCK Edge to Data Out Invalid (Data Out Hold)–1.0–1.0 ns
1
Applies to all nonautomotive-grade devices when operated within either of these voltage ranges.
2
Applies to all nonautomotive-grade devices when operated within these voltage ranges.
3
All automotive-grade devices are within these specifications.
Figure 24. Serial Peripheral Interface (SPI) Port—Master Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM