Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 37 of 68 | July 2010
Parallel Peripheral Interface Timing
Table 29 and Figure 16 on Page 37, Figure 20 on Page 40, and
Figure 23 on Page 42 describe parallel peripheral interface
operations.
Table 29. Parallel Peripheral Interface Timing
Parameter MinMaxUnit
Timing Requirements
t
PCLKW
PPI_CLK Width
1
6.0 ns
t
PCLK
PPI_CLK Period
1
15.0 ns
Timing Requirements—GP Input and Frame Capture Modes
t
SFSPE
External Frame Sync Setup Before PPI_CLK 6.7 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.0 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 1.5 ns
Switching Characteristics—GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 8.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 ns
t
DDTPE
Tran smit Data Delay After PPI_CLK 8.0 ns
t
HDTPE
Tran smit Data Hold After PPI_CLK 1.8 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.
Figure 16. PPI GP Rx Mode with Internal Frame Sync Timing
Figure 17. PPI GP Rx Mode with External Frame Sync Timing
t
HDRPE
t
SDRPE
t
HOFSPE
FRAME SYNC
DRIVEN
DATA
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
DFSPE
t
PCLK
t
PCLKW
t
PCLK
t
SFSPE
DATA SAMPLED /
FRAME SYNC SAMPLED
DATA SAMPLED /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW