Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 33 of 68 | July 2010
Asynchronous Memory Write Cycle Timing
Table 25. Asynchronous Memory Write Cycle Timing
Parameter MinMaxUnit
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 0.0 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After C LKOUT 6.0 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 1.0 ns
t
DO
Output Delay After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, AWE.
6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 ns
Figure 12. Asynchronous Memory Write Cycle Timing
SETUP
2 CYCLES
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
t
DO
t
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA 15–0
t
SARDY
t
SARDY
t
DDAT
t
ENDAT
t
HARDY
t
HO
t
DO
t
HARDY