Datasheet

Rev. I|Page 32 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
Asynchronous Memory Read Cycle Timing
Table 24. Asynchronous Memory Read Cycle Timing
Parameter MinMaxUnit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 0.8 ns
t
SARDY
ARDY Setup Before CLKOUT 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 0.0 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 ns
Figure 11. Asynchronous Memory Read Cycle Timing
t
HARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
t
DO
t
HARDY
t
SARDY
t
SDAT
t
HDAT
t
SARDY
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t
HO