Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I|Page 31 of 68 | July 2010
TIMING SPECIFICATIONS
Component specifications are subject to change
without notice.
Clock and Reset Timing
Table 22. Clock Input and Reset Timing
Parameter MinMaxUnit
Timing Requirements
t
CKIN
CLKIN Period
1, 2, 3, 4
1
Combinations of the CLKIN frequency and the PLL clock multiplier must not exceed the allowed f
VCO
, f
CCLK
, and f
SCLK
settings discussed in Table 10 through Table 14. Since
by default the PLL is multiplying the CLKIN frequency by 10, 300 MHz and 400 MHz speed grade parts can not use the full CLKIN period range.
2
Applies to PLL bypass mode and PLL non bypass mode.
3
CLKIN frequency must not change on the fly.
4
If the DF bit in the PLL_CTL register is set, then the maximum t
CKIN
period is 50 ns.
20.0100.0 ns
t
CKINL
CLKIN Low Pulse 8.0 ns
t
CKINH
CLKIN High Pulse 8.0 ns
t
BUFDLAY
CLKIN to CLKBUF Delay 10 ns
t
WRST
RESET Asserted Pulse Width Low 11 × t
CKIN
ns
t
NOBOOT
RESET Deassertion to First External Access Delay
5
5
Applies when processor is configured in No Boot Mode (BMODE2-0 = b#000).
3 × t
CKIN
5 × t
CKIN
ns
Figure 9. Clock and Reset Timing
Table 23. Power-Up Reset Timing
Parameter MinMaxUnit
Timing Requirements
t
RST_IN_PWR
RESET Deasserted After the V
DDINT
, V
DDEXT
, V
DDRTC
, and CLKIN Pins Are Stable and
Within Specification
3500 × t
CKIN
ns
In Figure 10, V
DD_SUPPLIES
is V
DDINT
, V
DDEXT
, V
DDRTC
Figure 10. Power-Up Reset Timing
CLKIN
t
WRST
t
CKIN
t
CKINL
t
CKINH
t
BUFDLAY
t
BUFDLAY
RESET
CLKBUF
t
NOBOOT
RESET
t
RST_IN_PWR
CLKIN
V
DD_SUPPLIES