Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I | Page 27 of 68 | July 2010
C
IN
Input
Capacitance
13, 14
f
IN
= 1 MHz, T
AMBIENT
=
25°C, V
IN
= 2.5 V
88pF
I
DD-IDLE
V
DDINT
Current in
Idle
V
DDINT
= 1.0 V, f
CCLK
= 50
MHz,
T
J
= 25°C, ASF = 0.43
14 24 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.14 V,
f
CCLK
=300MHz, T
J
=
25°C, ASF = 1.00
100 113 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.14 V,
f
CCLK
=400MHz, T
J
=
25°C, ASF = 1.00
125 138 mA
I
DDDEEPSLEEP
15
V
DDINT
Current in
Deep Sleep
Mode
V
DDINT
= 1.0 V, f
CCLK
= 0
MHz,
T
J
= 25°C, ASF = 0.00
616mA
I
DDSLEEP
V
DDINT
Current in
Sleep Mode
V
DDINT
= 1.0 V, f
SCLK
= 25
MHz,
T
J
= 25°C
9.5 19.5 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.20 V,
f
CCLK
=533MHz, T
J
=
25°C, ASF = 1.00
185 mA
I
DD-TYP
V
DDINT
Current V
DDINT
= 1.30 V,
f
CCLK
=600MHz, T
J
=
25°C, ASF = 1.00
227 mA
I
DDHIBERNATE
15, 16
V
DDEXT
Current in
Hibernate State
V
DDEXT
= 3.60 V,
CLKIN=0 MHz,
T
J
=maximum, with
voltage regulator off
(V
DDINT
=0 V)
50 100 50 100 μA
I
DDRTC
V
DDRTC
Current V
DDRTC
= 3.3 V, T
J
= 25°C 20 20 μA
I
DDDEEPSLEEP
15
V
DDINT
Current in
Deep Sleep
Mode
f
CCLK
= 0 MHz, f
SCLK
=0
MHz
Table 16 Table 15 mA
I
DDSLEEP
15, 17
V
DDINT
Current in
Sleep Mode
f
CCLK
= 0 MHz, f
SCLK
> 0
MHz
I
DDDEEPSLEEP
+ (0.14
× V
DDINT
× f
SCLK
)
I
DDDEEPSLEEP
+ (0.14
× V
DDINT
× f
SCLK
)
mA
I
DDINT
18
V
DDINT
Current f
CCLK
> 0 MHz, f
SCLK
> 0
MHz
I
DDSLEEP
+
(Table 18 × ASF)
I
DDSLEEP
+
(Table 18 × ASF)
mA
1
Applies to all 300 MHz and 400 MHz speed grade models. See Ordering Guide on Page 68.
2
Applies to all 500 MHz, 533 MHz, and 600 MHz speed grade models. See Ordering Guide on Page 68.
3
Applies to all output and bidirectional pins except port F pins, port G pins, and port H pins.
4
Applies to port F pins PF7–0.
5
Applies to port F pins PF15–8, all port G pins, and all port H pins.
6
Maximum combined current for Port F7–0.
7
Maximum total current for all port F, port G, and port H pins.
8
Applies to all input pins except PJ4.
9
Applies to input pin PJ4 only.
10
Applies to JTAG input pins (TCK, TDI, TMS, TRST).
11
Applies to three-statable pins.
12
Applies to bidirectional pins PJ2 and PJ3.
13
Applies to all signal pins.
14
Guaranteed, but not tested.
15
See the ADSP-BF537 Blackfin Processor Hardware Reference Manual for definition of sleep, deep sleep, and hibernate operating modes.
16
CLKIN must be tied to V
DDEXT
or GND during hibernate.
17
In the equations, the f
SCLK
parameter is the system clock in MHz.
18
See Table 17 for the list of I
DDINT
power vectors covered.
300 MHz/400 MHz
1
500 MHz/533 MHz/600 MHz
2
Parameter Test Conditions Min Typ Max Min Typ Max Unit