Datasheet

ADSP-BF534/ADSP-BF536/ADSP-BF537
Rev. I | Page 25 of 68 | July 2010
Table 10 through Table 12 describe the voltage/frequency
requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537
processor clocks. Take care in selecting MSEL, SSEL, and CSEL
ratios so as not to exceed the maximum core clock and system
clock. Table 13 describes phase-locked loop operating
conditions.
Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades
1
Parameter Internal Regulator Setting Max Unit
f
CCLK
Core Clock Frequency (V
DDINT
=1.30 V Minimum)
2
1.30 V 600 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 1.20 V Minimum)
3
1.25 V 533 MHz
f
CCLK
Core Clock Frequency (V
DDINT
=1.14 V Minimum) 1.20 V 500 MHz
f
CCLK
Core Clock Frequency (V
DDINT
=1.045 V Minimum) 1.10 V 444 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 400 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 333 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
1
See Ordering Guide on Page 68.
2
Applies to 600 MHz models only. See Ordering Guide on Page 68.
3
Applies to 533 MHz and 600 MHz models only. See Ordering Guide on Page 68.
Table 11. Core Clock Requirements—400 MHz Speed Grade
1
120°C ≥ T
J
> 105°C All
2
Other T
J
UnitParameter Internal Regulator Setting Max Max
f
CCLK
Core Clock Frequency (V
DDINT
=1.14 V Minimum) 1.20 V 400 400 MHz
f
CCLK
Core Clock Frequency (V
DDINT
=1.045 V Minimum) 1.10 V 333 363 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 295 333 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 280 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 250 MHz
1
See Ordering Guide on Page 68.
2
See Operating Conditions on Page 24.
Table 12. Core Clock Requirements—300 MHz Speed Grade
1
Parameter Internal Regulator Setting Max Unit
f
CCLK
Core Clock Frequency (V
DDINT
=1.14 V Minimum) 1.20 V 300 MHz
f
CCLK
Core Clock Frequency (V
DDINT
=1.045 V Minimum) 1.10 V 255 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.95 V Minimum) 1.00 V 210 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.85 V Minimum) 0.90 V 180 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.8 V Minimum) 0.85 V 160 MHz
1
See Ordering Guide on Page 68.
Table 13. Phase-Locked Loop Operating Conditions
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency 50 Max f
CCLK
MHz
Table 14. System Clock Requirements
Parameter Condition Max Unit
f
SCLK
1
V
DDEXT
= 3.3 V or 2.5 V, V
DDINT
≥ 1.14 V 133
2
MHz
f
SCLK
1
V
DDEXT
= 3.3 V or 2.5 V, V
DDINT
< 1.14 V 100 MHz
1
f
SCLK
must be less than or equal to f
CCLK
and is subject to additional restrictions for SDRAM interface operation. See Table 27 on Page 35.
2
Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 27 on Page 35.