Datasheet

Rev. I | Page 22 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
Port H: GPIO/10/100 Ethernet MAC (On
ADSP-BF534, these pins are GPIO only)
PH0 – GPIO/ETxD0 I/O GPIO/Ethernet MII or RMII Transmit D0 E
PH1 – GPIO/ETxD1 I/O GPIO/Ethernet MII or RMII Transmit D1 E
PH2 – GPIO/ETxD2 I/O GPIO/Ethernet MII Transmit D2 E
PH3 – GPIO/ETxD3 I/O GPIO/Ethernet MII Transmit D3 E
PH4 – GPIO/ETxEN I/O GPIO/Ethernet MII or RMII Transmit Enable E
PH5 – GPIO/MII TxCLK/RMII REF_CLK I/O GPIO/Ethernet MII Transmit Clock/RMII Reference Clock E
PH6 – GPIO/MII PHYINT
/RMII MDINT I/O GPIO/Ethernet MII PHY Interrupt/RMII Management Data Interrupt (This pin
should be pulled high when used as a hibernate wake-up.)
E
PH7 – GPIO/COL I/O GPIO/Ethernet Collision E
PH8 – GPIO/ERxD0 I/O GPIO/Ethernet MII or RMII Receive D0 E
PH9 – GPIO/ERxD1 I/O GPIO/Ethernet MII or RMII Receive D1 E
PH10 – GPIO/ERxD2 I/O GPIO/Ethernet MII Receive D2 E
PH11 – GPIO/ERxD3 I/O GPIO/Ethernet MII Receive D3 E
PH12 – GPIO/ERxDV/TACLK5 I/O GPIO/Ethernet MII Receive Data Valid/Alternate Timer5 Input Clock E
PH13 – GPIO/ERxCLK/TACLK6 I/O GPIO/Ethernet MII Receive Clock/Alternate Timer6 Input Clock E
PH14 – GPIO/ERxER/TACLK7 I/O GPIO/Ethernet MII or RMII Receive Error/Alternate Timer7 Input Clock E
PH15 – GPIO/MII CRS/RMII CRS_DV I/O GPIO/Ethernet MII Carrier Sense/Ethernet RMII Carrier Sense and Receive Data
Valid
E
Port J: SPORT0/TWI/SPI Select/CAN
PJ0 – MDC O Ethernet Management Channel Clock (On ADSP-BF534 processors, do not
connect this pin.)
E
PJ1 – MDIO I/O Ethernet Management Channel Serial Data (On ADSP-BF534 processors, tie this
pin to ground.)
E
PJ2 – SCL I/O TWI Serial Clock (This pin is an open-drain output and requires a pull-up
resistor.)
F
PJ3 – SDA I/O TWI Serial Data (This pin is an open-drain output and requires a pull-up
resistor.)
F
PJ4 – DR0SEC/CANRX/TACI0 I SPORT0 Receive Data Secondary/CAN Receive/Timer0 Alternate Input Capture
PJ5
– DT0SEC/CANTX/SPI SSEL7 O SPORT0 Transmit Data Secondary/CAN Transmit/SPI Slave Select Enable 7 C
PJ6 – RSCLK0/TACLK2 I/O SPORT0 Receive Serial Clock/Alternate Timer2 Clock Input D
PJ7 – RFS0/TACLK3 I/O SPORT0 Receive Frame Sync/Alternate Timer3 Clock Input C
PJ8 – DR0PRI/TACLK4 I SPORT0 Receive Data Primary/Alternate Timer4 Clock Input
PJ9 – TSCLK0/TACLK1 I/O SPORT0 Transmit Serial Clock/Alternate Timer1 Clock Input D
PJ10 – TFS0/SPI SSEL3 I/O SPORT0 Transmit Frame Sync/SPI Slave Select Enable 3 C
PJ11 – DT0PRI/SPI SSEL2 O SPORT0 Transmit Data Primary/SPI Slave Select Enable 2 C
Real-Time Clock
RTXI I RTC Crystal Input (This pin should be pulled low when not used.)
RTXO O RTC Crystal Output (Does not three-state in hibernate.)
JTAG Port
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
I JTAG Reset (This pin should be pulled low if the JTAG port is not used.)
EMU
O Emulation Output C
Table 9. Pin Descriptions (Continued)
Pin Name Type Function
Driver
Type
1