Datasheet

Rev. I | Page 2 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
TABLE OF CONTENTS
General Description ................................................. 3
Portable Low Power Architecture ............................. 3
System Integration ................................................ 3
Blackfin Processor Peripherals ................................. 3
Blackfin Processor Core .......................................... 4
Memory Architecture ............................................ 5
DMA Controllers .................................................. 8
Real-Time Clock ................................................... 9
Watchdog Timer .................................................. 9
Timers ............................................................... 9
Serial Ports (SPORTs) .......................................... 10
Serial Peripheral Interface (SPI) Port ....................... 10
UART Ports ...................................................... 10
Controller Area Network (CAN) ............................ 11
TWI Controller Interface ...................................... 11
10/100 Ethernet MAC .......................................... 11
Ports ................................................................ 12
Parallel Peripheral Interface (PPI) ........................... 12
Dynamic Power Management ................................ 13
Voltage Regulation .............................................. 14
Clock Signals ..................................................... 15
Booting Modes ................................................... 16
Instruction Set Description ................................... 17
Development Tools .............................................. 17
Designing an Emulator-Compatible Processor Board ... 18
Related Documents .............................................. 19
Related Signal Chains ........................................... 19
Pin Descriptions .................................................... 20
Specifications ........................................................ 24
Operating Conditions ........................................... 24
Electrical Characteristics ....................................... 26
Absolute Maximum Ratings ................................... 30
ESD Sensitivity ................................................... 30
Package Information ............................................ 30
Timing Specifications ........................................... 31
Output Drive Currents ......................................... 51
Test Conditions .................................................. 53
Thermal Characteristics ........................................ 57
182-Ball CSP_BGA Ball Assignment ........................... 58
208-Ball CSP_BGA Ball Assignment ........................... 61
Outline Dimensions ................................................ 64
Surface-Mount Design .......................................... 66
Automotive Products .............................................. 67
Ordering Guide ..................................................... 68
REVISION HISTORY
7/10—Rev. H to Rev. I
Corrected all document errata.
Replaced incorrect Figure 5, Voltage Regulator Circuit ... 14
Replaced incorrect Figure 13, External Port Bus Request and
Grant Cycle Timing ................................................ 34
To view product/process change notifications (PCNs) related to
this data sheet revision, please visit the processor’s product page
on the www.analog.com website and use the View PCN link.