Datasheet

Rev. I | Page 14 of 68 | July 2010
ADSP-BF534/ADSP-BF536/ADSP-BF537
processor to transition to the active mode. Assertion of RESET
while in deep sleep mode causes the processor to transition to
the full-on mode.
Hibernate State—Maximum Static Power Savings
The hibernate state maximizes static power savings by disabling
the voltage and clocks to the processor core (CCLK) and to all of
the synchronous peripherals (SCLK). The internal voltage regu-
lator for the processor can be shut off by writing b#00 to the
FREQ bits of the VR_CTL register. This disables both CCLK
and SCLK. Furthermore, it sets the internal power supply volt-
age (V
DDINT
) to 0 V to provide the greatest power savings. To
preserve the processor state, prior to removing power, any criti-
cal information stored internally (memory contents, register
contents, etc.) must be written to a nonvolatile storage device.
Since V
DDEXT
is still supplied in this state, all of the external pins
three-state, unless otherwise specified. This allows other devices
that are connected to the processor to still have power applied
without drawing unwanted current.
The Ethernet or CAN modules can wake up the internal supply
regulator. If the PH6 pin does not connect as the PHYINT
sig-
nal to an external PHY device, it can be pulled low by any other
device to wake the processor up. The regulator can also be
woken up by a real-time clock wake-up event or by asserting the
RESET
pin. All hibernate wake-up events initiate the hardware
reset sequence. Individual sources are enabled by the VR_CTL
register.
With the exception of the VR_CTL and the RTC registers, all
internal registers and memories lose their content in the hiber-
nate state. State variables can be held in external SRAM or
SDRAM. The SCKELOW bit in the VR_CTL register provides a
means of waking from hibernate state without disrupting a self-
refreshing SDRAM, provided that there is also an external pull-
down on the SCKE pin.
Power Savings
As shown in Table 5, the processors support three different
power domains which maximizes flexibility, while maintaining
compliance with industry standards and conventions. By isolat-
ing the internal logic of the processor into its own power
domain, separate from the RTC and other I/O, the processor
can take advantage of dynamic power management, without
affecting the RTC or other I/O devices. There are no sequencing
requirements for the various power domains.
The dynamic power management feature allows both the pro-
cessor’s input voltage (V
DDINT
) and clock frequency (f
CCLK
) to be
dynamically controlled.
The power dissipated by a processor is largely a function of its
clock frequency and the square of the operating voltage. For
example, reducing the clock frequency by 25% results in a 25%
reduction in power dissipation, while reducing the voltage by
25% reduces power dissipation by more than 40%. Further,
these power savings are additive, in that if the clock frequency
and supply voltage are both reduced, the power savings can be
dramatic, as shown in the following equations.
The power savings factor (PSF) is calculated as:
where:
f
CCLKNOM
is the nominal core clock frequency
f
CCLKRED
is the reduced core clock frequency
V
DDINTNOM
is the nominal internal supply voltage
V
DDINTRED
is the reduced internal supply voltage
t
NOM
is the duration running at f
CCLKNOM
t
RED
is the duration running at f
CCLKRED
The percent power savings is calculated as
VOLTAGE REGULATION
The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pro-
vide an on-chip voltage regulator that can generate appropriate
V
DDINT
voltage levels from the V
DDEXT
supply. See Operating
Conditions on Page 24 for regulator tolerances and acceptable
V
DDEXT
ranges for specific models.
Table 5. Power Domains
Power Domain V
DD
Range
All internal logic, except RTC V
DDINT
RTC internal logic and crystal I/O V
DDRTC
All other I/O V
DDEXT
Figure 5. Voltage Regulator Circuit
PSF
f
CCLKRED
f
CCLKNOM
---------------------
V
DDINTRED
V
DDINTNOM
--------------------------


2
×
t
RED
t
NOM
-----------


×


=
% power savings 1 PSF–()100%×=
V
DDEXT
(LOW-INDUCTANCE)
V
DDINT
VR
OUT
100μF
VR
OUT
GND
SHORT AND LOW-
INDUCTANCE WIRE
V
DDEXT
+
+
+
100μF
100μF
10μF
LOW ESR
100nF
SET OF DECOUPLING
CAPACITORS
FDS9431A
ZHCS1000
NOTE: DESIGNER SHOULD MINIMIZE
TRACE LENGTH TO FDS9431A.
10μH