Blackfin Embedded Processor ADSP-BF534/ADSP-BF536/ADSP-BF537 FEATURES PERIPHERALS Up to 600 MHz high performance Blackfin processor Three 16-bit MACs, two 40-bit ALUs, four 8-bit video ALUs, 40-bit shifter RISC-like register and instruction model for ease of programming and compiler-friendly support Advanced debug, trace, and performance monitoring Wide range of operating voltages (see Operating Conditions on Page 24) Qualified for Automotive Applications (see Automotive Products on Page 67) Programmable
ADSP-BF534/ADSP-BF536/ADSP-BF537 TABLE OF CONTENTS General Description ................................................. 3 Development Tools .............................................. 17 Portable Low Power Architecture ............................. 3 Designing an Emulator-Compatible Processor Board ... 18 System Integration ................................................ 3 Related Documents .............................................. 19 Blackfin Processor Peripherals ..........................
ADSP-BF534/ADSP-BF536/ADSP-BF537 GENERAL DESCRIPTION The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors are members of the Blackfin® family of products, incorporating the Analog Devices, Inc./Intel Micro Signal Architecture (MSA). Blackfin processors combine a dual-MAC, state-of-the-art signal processing engine, the advantages of a clean, orthogonal RISC-like microprocessor instruction set, and single-instruction, multiple-data (SIMD) multimedia capabilities into a single instruction-set architecture.
ADSP-BF534/ADSP-BF536/ADSP-BF537 BLACKFIN PROCESSOR CORE instructions include byte alignment and packing operations, 16-bit and 8-bit adds with clipping, 8-bit average operations, and 8-bit subtract/absolute value/accumulate (SAA) operations. Also provided are the compare/select and vector search instructions. As shown in Figure 2, the Blackfin processor core contains two 16-bit multipliers, two 40-bit accumulators, two 40-bit ALUs, four video ALUs, and a 40-bit shifter.
ADSP-BF534/ADSP-BF536/ADSP-BF537 The address arithmetic unit provides two addresses for simultaneous dual fetches from memory. It contains a multiported register file consisting of four sets of 32-bit index, modify, length, and base registers (for circular buffering), and eight additional 32-bit pointer registers (for C-style indexed stack manipulation). The memory DMA controller provides high bandwidth datamovement capability.
ADSP-BF534/ADSP-BF536/ADSP-BF537 ADSP-BF534/ADSP-BF537 MEMORY MAP ADSP-BF536 MEMORY MAP 0xFFFF FFFF 0xFFFF FFFF CORE MMR REGISTERS (2M BYTES) CORE MMR REGISTERS (2M BYTES) 0xFFE0 0000 0xFFE0 0000 SYSTEM MMR REGISTERS (2M BYTES) SYSTEM MMR REGISTERS (2M BYTES) 0xFFC0 0000 0xFFC0 0000 RESERVED RESERVED SCRATCHPAD SRAM (4K BYTES) SCRATCHPAD SRAM (4K BYTES) 0xFFB0 0000 0xFFB0 0000 RESERVED 0xFFA1 4000 INTERNAL MEMORY MAP RESERVED 0xFFA1 4000 INSTRUCTION SRAM/CACHE (16K BYTES) 0xFFA1 0000 RESE
ADSP-BF534/ADSP-BF536/ADSP-BF537 Conceptually, interrupts from the peripherals enter into the SIC, and are then routed directly into the general-purpose interrupts of the CEC. Core Event Controller (CEC) The CEC supports nine general-purpose interrupts (IVG15–7), in addition to the dedicated interrupt and exception events.
ADSP-BF534/ADSP-BF536/ADSP-BF537 • SIC interrupt wake-up enable register (SIC_IWR) – By enabling the corresponding bit in this register, a peripheral can be configured to wake up the processor, should the core be idled when the event is generated. (For more information, see Dynamic Power Management on Page 13.) Table 3.
ADSP-BF534/ADSP-BF536/ADSP-BF537 In addition to the dedicated peripheral DMA channels, there are two memory DMA channels provided for transfers between the various memories of the processor system. This enables transfers of blocks of data between any of the memories—including external SDRAM, ROM, SRAM, and flash memory—with minimal processor intervention. Memory DMA transfers can be controlled by a very flexible descriptor-based methodology or by a standard register-based autobuffer mechanism.
ADSP-BF534/ADSP-BF536/ADSP-BF537 SERIAL PORTS (SPORTs) The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors incorporate two dual-channel synchronous serial ports (SPORT0 and SPORT1) for serial and multiprocessor communications. The SPORTs support the following features: • I2S capable operation. • Bidirectional operation – Each SPORT has two sets of independent transmit and receive pins, enabling eight channels of I2S stereo audio.
ADSP-BF534/ADSP-BF536/ADSP-BF537 In conjunction with the general-purpose timer functions, autobaud detection is supported. The capabilities of the UARTs are further extended with support for the infrared data association (IrDA®) serial infrared physical layer link specification (SIR) protocol. CONTROLLER AREA NETWORK (CAN) The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors offer a CAN controller that is a communication controller implementing the CAN 2.0B (active) protocol.
ADSP-BF534/ADSP-BF536/ADSP-BF537 GPIO pins defined as inputs can be configured to generate hardware interrupts, while output pins can be triggered by software interrupts. • Programmable Rx address filters, including a 64-bit address hash table for multicast and/or unicast frames, and programmable filter modes for broadcast, multicast, unicast, control, and damaged frames.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Frame Capture Mode Full-On Operating Mode—Maximum Performance Frame capture mode allows the video source(s) to act as a slave (for frame capture for example). The ADSP-BF534/ ADSP-BF536/ADSP-BF537 processors control when to read from the video source(s). PPI_FS1 is an HSYNC output and PPI_FS2 is a VSYNC output. In the full-on mode, the PLL is enabled and is not bypassed, providing capability for maximum operational frequency.
ADSP-BF534/ADSP-BF536/ADSP-BF537 processor to transition to the active mode. Assertion of RESET while in deep sleep mode causes the processor to transition to the full-on mode. Hibernate State—Maximum Static Power Savings The hibernate state maximizes static power savings by disabling the voltage and clocks to the processor core (CCLK) and to all of the synchronous peripherals (SCLK). The internal voltage regulator for the processor can be shut off by writing b#00 to the FREQ bits of the VR_CTL register.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Figure 5 shows the typical external components required to complete the power management system. The regulator controls the internal logic voltage levels and is programmable with the voltage regulator control register (VR_CTL) in increments of 50 mV. To reduce standby power consumption, the internal voltage regulator can be programmed to remove power to the processor core while keeping I/O power supplied.
ADSP-BF534/ADSP-BF536/ADSP-BF537 ence signal in other timing specifications as well. While active by default, it can be disabled using the EBIU_SDGCTL and EBIU_AMGCTL registers. All on-chip peripherals are clocked by the system clock (SCLK). The system clock frequency is programmable by means of the SSEL3–0 bits of the PLL_DIV register. The values programmed into the SSEL fields define a divide ratio between the PLL output (VCO) and the system clock. SCLK divider values are 1 through 15.
ADSP-BF534/ADSP-BF536/ADSP-BF537 (8 bits data, 1 start bit, 1 stop bit, no parity bit) on the RXD pin to determine the bit rate. It then replies with an acknowledgement that is composed of 4 bytes: 0xBF, the value of UART_DLL, the value of UART_DLH, and 0x00. The host can then download the boot stream. When the processor needs to hold off the host, it deasserts CTS. Therefore, the host must monitor this signal.
ADSP-BF534/ADSP-BF536/ADSP-BF537 efficiently. By using the profiler, the programmer can focus on those areas in the program that impact performance and take corrective action. Debugging both C/C++ and assembly programs with the VisualDSP++ debugger, programmers can • View mixed C/C++ and assembly code (interleaved source and object information). • Insert breakpoints. • Set conditional breakpoints on registers, memory, and stacks. • Trace instruction execution. Analog Devices emulators use the IEEE 1149.
ADSP-BF534/ADSP-BF536/ADSP-BF537 RELATED DOCUMENTS The following publications that describe the ADSP-BF534/ ADSP-BF536/ADSP-BF537 processors (and related processors) can be ordered from any Analog Devices sales office or accessed electronically on our website: • Getting Started with Blackfin Processors • ADSP-BF537 Blackfin Processor Hardware Reference • ADSP-BF53x/ADSP-BF56x Blackfin Processor Programming Reference • ADSP-BF534/ADSP-BF536/ADSP-BF537 Blackfin Processor Anomaly List RELATED SIGNAL CHAINS A
ADSP-BF534/ADSP-BF536/ADSP-BF537 PIN DESCRIPTIONS The ADSP-BF534/ADSP-BF536/ADSP-BF537 processors pin definitions are listed in Table 9. In order to maintain maximum functionality and reduce package size and pin count, some pins have dual, multiplexed functions. In cases where pin function is reconfigurable, the default state is shown in plain text, while the alternate function is shown in italics. Pins shown with an asterisk after their name (*) offer high source/high sink current capabilities.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 9.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 9.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 9. Pin Descriptions (Continued) Type Function Driver Type1 I O O Clock/Crystal Input Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.) Buffered XTAL Output (If enabled, does not three-state during hibernate.) E I I I Reset Nonmaskable Interrupt (This pin should be pulled high when not used.) Boot Mode Strap 2-0 (These pins must be pulled to the state required for the desired boot mode.
ADSP-BF534/ADSP-BF536/ADSP-BF537 SPECIFICATIONS Note that component specifications are subject to change without notice. OPERATING CONDITIONS Parameter VDDINT Internal Supply Voltage1 VDDINT VDDINT VDDINT Internal Supply Voltage1 Internal Supply Voltage1 Internal Supply Voltage1 VDDEXT VDDEXT External Supply Voltage External Supply Voltage VDDRTC TJ Real-Time Clock Power Supply Voltage High Level Input Voltage3, 4 High Level Input Voltage5 5.0 V Tolerant Pins, High Level Input Voltage6 5.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 10 through Table 12 describe the voltage/frequency requirements for the ADSP-BF534/ADSP-BF536/ADSP-BF537 processor clocks. Take care in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the maximum core clock and system clock. Table 13 describes phase-locked loop operating conditions. Table 10. Core Clock Requirements—500 MHz, 533 MHz, and 600 MHz Speed Grades1 Parameter fCCLK Core Clock Frequency (VDDINT =1.
ADSP-BF534/ADSP-BF536/ADSP-BF537 ELECTRICAL CHARACTERISTICS Parameter VOH3 VOH4 VOH5 IOH6 300 MHz/400 MHz1 Min Typ Max VDDEXT – 0.5 Test Conditions High Level VDDEXT = 2.5 V/3.0 V/ Output Voltage 3.3 V ± 10%, IOH = –0.5 mA VDDEXT = 3.3 V ± 10%, VDDEXT – 0.5 IOH = –8 mA VDDEXT = 2.5 V/3.0 V ± VDDEXT – 0.5 10%, IOH = –6 mA VDDEXT = 2.5 V/3.0 V/ VDDEXT – 0.5 3.3 V ± 10%, IOH = –2.0 mA High Level VOH = VDDEXT – 0.5 V Min Output Current IOH7 VOH = VDDEXT – 0.5 V Min VOL3 Low Level VDDEXT = 2.5 V/3.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Parameter CIN IDD-IDLE Input Capacitance13, 14 VDDINT Current in Idle IDD-TYP VDDINT Current IDD-TYP VDDINT Current IDDDEEPSLEEP15 VDDINT Current in Deep Sleep Mode VDDINT Current in Sleep Mode IDDSLEEP IDD-TYP VDDINT Current IDD-TYP VDDINT Current IDDHIBERNATE15, 16 VDDEXT Current in Hibernate State IDDRTC IDDDEEPSLEEP15 IDDSLEEP15, 17 IDDINT18 Test Conditions Min fIN = 1 MHz, TAMBIENT = 25°C, VIN = 2.5 V VDDINT = 1.0 V, fCCLK = 50 MHz, TJ = 25°C, ASF = 0.
ADSP-BF534/ADSP-BF536/ADSP-BF537 System designers should refer to Estimating Power for the ADSP-BF534/BF536/BF537 Blackfin Processors (EE-297), which provides detailed information for optimizing designs for lowest power. All topics discussed in this section are described in detail in EE-297. Total power dissipation has two components: 1. Static, including leakage current 2.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 17. Activity Scaling Factors IDDINT Power Vector1 IDD-PEAK IDD-HIGH IDD-TYP IDD-APP IDD-NOP IDD-IDLE 1 2 Activity Scaling Factor (ASF)2 1.33 1.29 1.00 0.88 0.72 0.43 See EE-297 for power vector definitions. All ASF values determined using a 10:1 CCLK:SCLK ratio. Table 18. Dynamic Current (mA, with ASF = 1.0)1 Voltage (VDDINT) Frequency (MHz) 50 100 200 300 400 500 533 600 1 0.80 V 11.0 27.9 36.9 N/A N/A N/A N/A N/A 0.85 V 13.7 22.7 42.6 61.5 N/A N/A N/A N/A 0.
ADSP-BF534/ADSP-BF536/ADSP-BF537 ABSOLUTE MAXIMUM RATINGS PACKAGE INFORMATION Stresses greater than those listed in Table 19 may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions greater than those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ADSP-BF534/ADSP-BF536/ADSP-BF537 TIMING SPECIFICATIONS Component specifications are subject to change without notice. Clock and Reset Timing Table 22. Clock Input and Reset Timing Parameter Timing Requirements tCKIN CLKIN Period1, 2, 3, 4 tCKINL CLKIN Low Pulse tCKINH CLKIN High Pulse tBUFDLAY CLKIN to CLKBUF Delay RESET Asserted Pulse Width Low tWRST tNOBOOT RESET Deassertion to First External Access Delay5 Min Max Unit 20.0 8.0 8.0 100.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Asynchronous Memory Read Cycle Timing Table 24. Asynchronous Memory Read Cycle Timing Parameter Timing Requirements tSDAT DATA15–0 Setup Before CLKOUT tHDAT DATA15–0 Hold After CLKOUT tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO 1 Min Max 2.1 0.8 4.0 0.0 ns ns ns ns 6.0 0.8 Output pins include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Asynchronous Memory Write Cycle Timing Table 25. Asynchronous Memory Write Cycle Timing Parameter Timing Requirements tSARDY ARDY Setup Before CLKOUT tHARDY ARDY Hold After CLKOUT Switching Characteristics tDDAT DATA15–0 Disable After CLKOUT tENDAT DATA15–0 Enable After CLKOUT tDO Output Delay After CLKOUT1 Output Hold After CLKOUT 1 tHO 1 Min 4.0 0.0 1.0 6.0 0.
ADSP-BF534/ADSP-BF536/ADSP-BF537 External Port Bus Request and Grant Cycle Timing Table 26 and Figure 13 describe external port bus request and bus grant operations. Table 26.
ADSP-BF534/ADSP-BF536/ADSP-BF537 SDRAM Interface Timing Table 27.
ADSP-BF534/ADSP-BF536/ADSP-BF537 External DMA Request Timing Table 28 and Figure 15 describe the external DMA request operations. Table 28. External DMA Request Timing Parameter Timing Requirements tDR DMARx Asserted to CLKOUT High Setup tDH CLKOUT High to DMARx Deasserted Hold Time tDMARACT DMARx Active Pulse Width tDMARINACT DMARx Inactive Pulse Width Min 6.0 0.0 1.0 × tSCLK 1.75 × tSCLK CLKOUT tDR DMAR0/1 (ACTIVE LOW) DMAR0/1 (ACTIVE HIGH) tDH tDMARACT tDMARINACT tDMARACT tDMARINACT Figure 15.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Parallel Peripheral Interface Timing Table 29 and Figure 16 on Page 37, Figure 20 on Page 40, and Figure 23 on Page 42 describe parallel peripheral interface operations. Table 29.
ADSP-BF534/ADSP-BF536/ADSP-BF537 FRAME SYNC DRIVEN DATA DRIVEN DATA DRIVEN tPCLK PPI_CLK tHOFSPE tDFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 18. PPI GP Tx Mode with Internal Frame Sync Timing DATA DRIVEN / FRAME SYNC SAMPLED PPI_CLK tSFSPE tHFSPE tPCLKW PPI_FS1/2 tDDTPE tHDTPE PPI_DATA Figure 19. PPI GP Tx Mode with External Frame Sync Timing Rev.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Serial Port Timing Table 30 through Table 33 on Page 42 and Figure 20 on Page 40 through Figure 23 on Page 42 describe serial port operations. Table 30.
ADSP-BF534/ADSP-BF536/ADSP-BF537 DATA RECEIVE—INTERNAL CLOCK DATA RECEIVE—EXTERNAL CLOCK DRIVE EDGE DRIVE EDGE SAMPLE EDGE SAMPLE EDGE tSCLKE tSCLKEW tSCLKIW RSCLKx RSCLKx tDFSE tDFSI tHOFSI tHOFSE RFSx (OUTPUT) RFSx (OUTPUT) tSFSI tHFSI RFSx (INPUT) tSFSE tHFSE tSDRE tHDRE RFSx (INPUT) tSDRI tHDRI DRx DRx DATA TRANSMIT—INTERNAL CLOCK DATA TRANSMIT—EXTERNAL CLOCK DRIVE EDGE SAMPLE EDGE DRIVE EDGE tSCLKIW SAMPLE EDGE t SCLKEW TSCLKx tSCLKE TSCLKx tD FSI tDFSE tHOFSI tH
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 32. Serial Ports—Enable and Three-State Parameter Switching Characteristics tDTENE Data Enable Delay from External TSCLKx1 Data Disable Delay from External TSCLKx1 tDDTTE tDTENI Data Enable Delay from Internal TSCLKx1 tDDTTI Data Disable Delay from Internal TSCLKx1 1 Min 0 10.0 –2.0 3.0 Referenced to drive edge. DRIVE EDGE DRIVE EDGE TSCLKx tDTENE/I tDDTTE/I DTx Figure 22. Enable and Three-State Rev.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 33. External Late Frame Sync Parameter Switching Characteristics tDDTLFSE Data Delay from Late External TFSx or External RFSx with MCMEN = 1, MFD = 01, 2 Data Enable from Late FS or MCMEN = 1, MFD = 01, 2 tDTENLFS 1 2 MCMEN = 1, TFSx enable and TFSx valid follow tDDTENFS and tDDTLFS. If external RFSx/TFSx setup to RSCLKx/TSCLKx > tSCLKE/2, then tDDTE/I and tDTENE/I apply, otherwise tDDTLFSE and tDTENLFS apply.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Serial Peripheral Interface Port—Master Timing Table 34 and Figure 24 describe SPI port master operations. Table 34.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Serial Peripheral Interface Port—Slave Timing Table 35 and Figure 25 describe SPI port slave operations. Table 35.
ADSP-BF534/ADSP-BF536/ADSP-BF537 General-Purpose Port Timing Table 36 and Figure 26 describe general-purpose port operations. Table 36. General-Purpose Port Timing Parameter Timing Requirement tWFI General-Purpose Port Pin Input Pulse Width Switching Characteristic tGPOD General-Purpose Port Pin Output Delay from CLKOUT Low Min tSCLK + 1 0 CLKOUT tGPOD GPIO OUTPUT tWFI GPIO INPUT Figure 26.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Timer Clock Timing Table 37 and Figure 27 describe timer clock timing. Table 37. Timer Clock Timing Parameter Switching Characteristic tTODP Timer Output Update Delay After PPI_CLK High Min Max Unit 12 ns PPI_CLK tTODP TMRx OUTPUT Figure 27. Timer Clock Timing Timer Cycle Timing Table 38 and Figure 28 describe timer expired operations.
ADSP-BF534/ADSP-BF536/ADSP-BF537 JTAG Test and Emulation Port Timing Table 39 and Figure 29 describe JTAG port operations. Table 39.
ADSP-BF534/ADSP-BF536/ADSP-BF537 10/100 Ethernet MAC Controller Timing Table 40 through Table 45 and Figure 30 through Figure 35 describe the 10/100 Ethernet MAC controller operations. This feature is only available on the ADSP-BF536 and ADSP-BF537 processors. Table 40.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 44. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal Parameter1, 2 tECOLH COL Pulse Width High tECOLL COL Pulse Width Low tECRSH tECRSL CRS Pulse Width High CRS Pulse Width Low Min tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tERxCLK × 1.5 tETxCLK × 1.5 tETxCLK × 1.5 Max Unit ns ns ns ns ns ns 1 MII/RMII asynchronous signals are COL, CRS. These signals are applicable in both MII and RMII modes.
ADSP-BF534/ADSP-BF536/ADSP-BF537 tREFCLK tREFCLKW RMII_REF_CLK ERxD1–0 ERxDV ERxER tREFCLKIS tREFCLKIH Figure 32. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal tREFCLK RMII_REF_CLK tREFCLKOH ETxD1–0 ETxEN tREFCLKOV Figure 33. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal MIICRS, COL tECRSH tECOLH tECRSL tECOLL Figure 34. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal MDC (OUTPUT) tMDCOH MDIO (OUTPUT) tMDCOV MDIO (INPUT) tMDIOS tMDCIH Figure 35.
ADSP-BF534/ADSP-BF536/ADSP-BF537 OUTPUT DRIVE CURRENTS Figure 36 through Figure 47 show typical current-voltage characteristics for the output drivers of the processors. The curves represent the current drive capability of the output drivers as a function of output voltage. See Table 9 on Page 20 for information about which driver type corresponds to a particular pin. 200 SOURCE CURRENT (mA) 100 120 VDDEXT = 2.25V @ 95°C 100 VDDEXT = 2.50V @ 25°C SOURCE CURRENT (mA) 80 VDDEXT = 2.
ADSP-BF534/ADSP-BF536/ADSP-BF537 100 80 80 SOURCE CURRENT (mA) 60 SOURCE CURRENT (mA) VDDEXT = 2.25V @ 95°C VDDEXT = 2.50V @ 25°C VDDEXT = 2.75V @ -40°C 40 VOH 20 0 -20 -40 VOL 60 VDDEXT = 3.0V @ 95°C VDDEXT = 3.3V @ 25°C 40 VDDEXT = 3.6V @ -40°C 20 VOH 0 -20 -40 VOL -60 -60 -80 -80 0 0.5 1.0 1.5 2.0 3.0 2.5 0 0.5 1.0 1.5 2.0 2.5 Figure 42. Drive Current D (Low VDDEXT) 4.0 0 VDDEXT = 3.0V @ 95°C VDDEXT = 2.25V @ 95°C VDDEXT = 3.3V @ 25°C VDDEXT = 3.
ADSP-BF534/ADSP-BF536/ADSP-BF537 TEST CONDITIONS Output Disable Time All timing parameters appearing in this data sheet were measured under the conditions described in this section. Figure 48 shows the measurement point for ac measurements (other than output enable/disable). The measurement point is VMEAS = VDDEXT/2. Output pins are considered to be disabled when they stop driving, go into a high impedance state, and start to decay from their output high or low voltage.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Capacitive Loading TESTER PIN ELECTRONICS 50Ω VLOAD T1 RISE AND FALL TIME ns (10% to 90%) 14 Output delays and holds are based on standard capacitive loads: 30 pF on all pins (see Figure 50). Figure 51 through Figure 60 on Page 56 show how output rise time varies with capacitance. The delay and hold specifications given should be derated by a factor derived from these figures. The graphs in these figures may not be linear outside the ranges shown.
ADSP-BF534/ADSP-BF536/ADSP-BF537 20 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 12 10 RISE TIME 8 FALL TIME 6 4 2 18 16 RISE TIME 14 12 FALL TIME 10 8 6 4 2 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 0 250 Figure 53. Typical Output Delay or Hold for Driver B at VDDEXT Min 0 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 56.
ADSP-BF534/ADSP-BF536/ADSP-BF537 36 RISE AND FALL TIME ns (10% to 90%) RISE AND FALL TIME ns (10% to 90%) 36 32 28 RISE TIME 24 20 FALL TIME 16 12 8 28 RISE TIME 24 20 16 FALL TIME 12 8 4 4 0 0 0 50 100 150 LOAD CAPACITANCE (pF) 200 0 250 Figure 59. Typical Output Delay or Hold for Driver E at VDDEXT Min 50 100 150 LOAD CAPACITANCE (pF) 200 250 Figure 61.
ADSP-BF534/ADSP-BF536/ADSP-BF537 THERMAL CHARACTERISTICS Table 46. Thermal Characteristics (182-Ball BGA) To determine the junction temperature on the application printed circuit board use: Parameter θJA θJMA θJMA θJB θJC ΨJT ΨJT ΨJT T J = T CASE + ( Ψ JT × P D ) where: TJ = Junction temperature (°C) TCASE = Case temperature (°C) measured by customer at top center of package. ΨJT = From Table 46 Values of θJA are provided for package comparison and printed circuit board design considerations.
ADSP-BF534/ADSP-BF536/ADSP-BF537 182-BALL CSP_BGA BALL ASSIGNMENT Table 49 lists the CSP_BGA ball assignment by signal mnemonic. Table 50 on Page 59 lists the CSP_BGA ball assignment by ball number. Table 49. 182-Ball CSP_BGA Ball Assignment (Alphabetically by Signal Mnemonic) Mnemonic ABE0 ABE1 ADDR1 ADDR10 ADDR11 ADDR12 ADDR13 ADDR14 ADDR15 ADDR16 ADDR17 ADDR18 ADDR19 ADDR2 ADDR3 ADDR4 ADDR5 ADDR6 ADDR7 ADDR8 ADDR9 AMS0 AMS1 AMS2 AMS3 AOE ARDY ARE AWE BG BGH BMODE0 BMODE1 BMODE2 BR CLKBUF CLKIN Ball No.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 50. 182-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No. A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 C1 C2 C3 C4 C5 C6 C7 C8 C9 Mnemonic VDDEXT PH11 PH12 PH13 PH14 PH15 CLKBUF RTXO RTXI GND XTAL CLKIN VROUT0 GND PH5 PH6 PH7 PH8 PH9 PH10 PJ1 PJ7 VDDRTC NMI PJ2 VROUT1 SCKE CLKOUT PG15 PH0 PH1 PH2 PH3 PH4 PJ0 PJ6 PJ9 Ball No.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Figure 63 shows the top view of the CSP_BGA ball configuration. Figure 64 shows the bottom view of the CSP_BGA ball configuration. 1 2 3 4 5 6 7 8 9 14 13 12 11 10 9 10 11 12 13 14 8 7 6 5 4 3 2 1 A A B B C C D D E E F F G G H H J J K K L L M M N N P P KEY: KEY: VDDINT VDDEXT GND I/O VDDRTC VROUT GND VDDRTC VDDEXT I/O VROUT Figure 64. 182-Ball CSP_BGA Configuration (Bottom View) Figure 63.
ADSP-BF534/ADSP-BF536/ADSP-BF537 208-BALL CSP_BGA BALL ASSIGNMENT Table 51 lists the CSP_BGA ball assignment by signal mnemonic. Table 52 on Page 62 lists the CSP_BGA ball assignment by ball number. Table 51.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Table 52 lists the CSP_BGA ball assignment by ball number. Table 51 on Page 61 lists the CSP_BGA ball assignment by signal mnemonic. Table 52. 208-Ball CSP_BGA Ball Assignment (Numerically by Ball Number) Ball No.
ADSP-BF534/ADSP-BF536/ADSP-BF537 Figure 65 shows the top view of the CSP_BGA ball configuration. Figure 66 shows the bottom view of the CSP_BGA ball configuration. 1 2 3 4 5 6 7 8 9 20 19 18 17 16 15 14 13 12 11 10 10 11 12 13 14 15 16 17 18 19 20 9 8 7 6 5 4 VDDEXT I/O A B C C D D E E F F G G H H J J K K L L M M N N P P R R T T U U V V W W Y Y VDDRTC VDDINT GND VDDRTC VROUT VDDEXT I/O VROUT Figure 66.
ADSP-BF534/ADSP-BF536/ADSP-BF537 OUTLINE DIMENSIONS Dimensions in Figure 67 and Figure 68 are shown in millimeters. A1 CORNER INDEX AREA 12.00 BSC SQ 14 13 12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G H J K L M N P PIN A1 INDICATOR LOCATION 10.40 BSC SQ 0.80 BSC TYP TOP VIEW BOTTOM VIEW 1.31 1.21 1.10 DETAIL A 1.70 MAX 0.25 MIN SEATING PLANE NOTES: 1. COMPLIANT TO JEDEC STANDARD MO-205-AE, EXCEPT FOR BALL DIAMETER. 2. CENTER DIMENSIONS ARE NOMINAL. 3. THE ACTUAL POSITION OF THE BALL GRID IS WITHIN 0.
ADSP-BF534/ADSP-BF536/ADSP-BF537 17.10 17.00 SQ 16.90 A1 CORNER INDEX AREA 20 18 16 14 12 10 8 6 4 2 19 17 15 13 11 9 7 5 3 1 A1 BALL CORNER A B C D E F G H J K L M N P R T U V W Y 15.20 BSC SQ 0.80 BSC TOP VIEW *1.75 BOTTOM VIEW DETAIL A 1.36 1.26 1.16 DETAIL A 1.61 1.46 0.35 NOM 0.30 MIN *0.50 0.45 0.40 BALL DIAMETER SEATING PLANE COPLANARITY 0.12 *COMPLIANT TO JEDEC STANDARDS MO-205-AM WITH EXCEPTION TO PACKAGE HEIGHT AND BALL DIAMETER. Figure 68.
ADSP-BF534/ADSP-BF536/ADSP-BF537 SURFACE-MOUNT DESIGN The following table is provided as an aid to PCB design. For industry-standard design recommendations, refer to IPC-7351, Generic Requirements for Surface Mount Design and Land Pattern Standard. Package 182-Ball CSP_BGA (BC-182) 208-Ball CSP_BGA (BC-208-2) Package Ball Attach Type Solder Mask Defined Solder Mask Defined Rev. I | Page 66 of 68 | Package Solder Mask Opening 0.40 mm diameter 0.40 mm diameter July 2010 Package Ball Pad Size 0.
ADSP-BF534/ADSP-BF536/ADSP-BF537 AUTOMOTIVE PRODUCTS The ADBF534W model is available with controlled manufacturing to support the quality and reliability requirements of automotive applications. Note that these automotive models may have specifications that differ from the commercial models and designers should review the Specifications section of this data sheet carefully. Only the automotive grade products shown in Table 53 are available for use in automotive applications.
ADSP-BF534/ADSP-BF536/ADSP-BF537 ORDERING GUIDE In the following table CSP_BGA = Chip Scale Package Ball Grid Array.
