Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 33 of 64 | August 2013
Figure 19. PPI GP Rx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
Figure 20. PPI GP Tx Mode with Internal Frame Sync Timing
Figure 21. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 1)
Figure 22. PPI GP Tx Mode with External Frame Sync Timing (PPI_CONTROL Bit 8 = 0)
t
PCLK
t
SFSPE
FRAME SYNC
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
HDRPE
t
SDRPE
t
PCLKW
DATA
SAMPLED
t
HOFSPE
FRAME SYNC
DRIVEN
DATA
DRIVEN
PPI_DATA
PPI_CLK
PPI_FS1/2
t
DFSPE
t
DDTPE
t
HDTPE
t
PCLK
t
PCLKW
DATA
DRIVEN
t
HDTPE
t
SFSPE
DATA DRIVEN /
FRAME SYNC SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
DDTPE
t
PCLK
t
PCLKW
t
HDTPE
t
SFSPE
DATA
DRIVEN
FRAME SYNC
SAMPLED
PPI_DATA
PPI_CLK
PPI_FS1/2
t
HFSPE
t
DDTPE
t
PCLK
t
PCLKW