Datasheet

ADSP-BF531/ADSP-BF532/ADSP-BF533
Rev. I | Page 29 of 64 | August 2013
Asynchronous Memory Write Cycle Timing
Table 24. Asynchronous Memory Write Cycle Timing
V
DDEXT
= 1.8 V V
DDEXT
= 2.5 V/3.3 V
Parameter Min Max Min Max Unit
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT 4.0 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 1.0 0.0 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT 6.0 6.0 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 1.0 1.0 ns
t
DO
Output Delay After CLKOUT
1
1
Output pins include AMS3–0, ABE1–0, ADDR19–1, DATA15–0, AOE, AWE.
6.0 6.0 ns
t
HO
Output Hold After CLKOUT
1
1.0 0.8 ns
Figure 14. Asynchronous Memory Write Cycle Timing
SETUP
2 CYCLES
PROGRAMMED
WRITE ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
t
DO
t
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
DATA 15–0
t
DO
t
SARDY
t
DDAT
t
ENDAT
t
HO
t
HARDY
t
HARDY
ARDY
t
SARDY