Datasheet

Rev. D | Page 76 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Output Disable Time Measurement
Output balls are considered to be disabled when they stop driv-
ing, go into a high impedance state, and start to decay from their
output high or low voltage. The output disable time t
DIS
is the
difference between t
DIS_MEASURED
and t
DECAY
as shown on the left
side of Figure 59.
The time for the voltage on the bus to decay by V is dependent
on the capacitive load C
L
and the load current I
L
. This decay
time can be approximated by the equation:
The time t
DECAY
is calculated with test loads C
L
and I
L
, and with
V equal to 0.25 V for V
DDEXT
/V
DDMEM
(nominal) = 2.5 V/3.3 V
and 0.15 V for V
DDEXT
/V
DDMEM
(nominal) = 1.8V.
The time t
DIS_MEASURED
is the interval from when the reference
signal switches, to when the output voltage decays V from the
measured output high or output low voltage.
Example System Hold Time Calculation
To determine the data output hold time in a particular system,
first calculate t
DECAY
using the equation given above. Choose V
to be the difference between the processor’s output voltage and
the input threshold for the device requiring the hold time. C
L
is
the total bus capacitance (per data line), and I
L
is the total leak-
age or three-state current (per data line). The hold time will be
t
DECAY
plus the various output disable times as specified in the
Timing Specifications on Page 39 (for example t
DSDAT
for an
SDRAM write cycle as shown in SDRAM Interface Timing on
Page 47).
Capacitive Loading
Output delays and holds are based on standard capacitive loads
of an average of 6 pF on all balls (see Figure 60). V
LOAD
is equal
to (V
DDEXT
/V
DDMEM
) /2. The graphs of Figure 61 through
Figure 72 show how output rise time varies with capacitance.
The delay and hold specifications given should be derated by a
factor derived from these figures. The graphs in these figures
may not be linear outside the ranges shown.
t
DIS
t
DIS_MEASURED
t
DECAY
–=
t
DECAY
C
L
VI
L
=
Figure 60. Equivalent Device Loading for AC Measurements
(Includes All Fixtures)
Figure 61. Driver Type A Typical Rise and Fall Times (10%–90%) vs.
Load Capacitance (1.8V V
DDEXT
/V
DDMEM
)
T1
ZO = 50Ω (impedance)
TD = 4.04 ± 1.18 ns
2pF
TESTER PIN ELECTRONICS
50Ω
0.5pF
70Ω
400Ω
45Ω
4pF
NOTES:
THE WORST CASE TRANSMISSION LINE DELAY IS SHOWN AND CAN BE USED
FOR THE OUTPUT TIMING ANALYSIS TO REFELECT THE TRANSMISSION LINE
EFFECT AND MUST BE CONSIDERED. THE TRANSMISSION LINE (TD) IS FOR
LOAD ONLY AND DOES NOT AFFECT THE DATA SHEET TIMING SPECIFICATIONS.
ANALOG DEVICES RECOMMENDS USING THE IBIS MODEL TIMING FOR A GIVEN
SYSTEM REQUIREMENT. IF NECESSARY, A SYSTEM MAY INCORPORATE
EXTERNAL DRIVERS TO COMPENSATE FOR ANY TIMING DIFFERENCES.
V
LOAD
DUT
OUTPUT
50Ω
6
RISE AND FALL TIME (10% TO 90%)
LOAD CAPACITANCE (pF)
0 50 100 150
12
10
0
2
4
8
200
t
RISE
t
FALL
t
RISE
= 1.8V @ 25 ° C
t
FALL
= 1.8V @ 25 ° C