Datasheet

Rev. D | Page 72 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
JTAG Test And Emulation Port Timing
Table 64 and Figure 42 describe JTAG port operations.
Table 64. JTAG Port Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
TCK
TCK Period 20 20 ns
t
STAP
TDI, TMS Setup Before TCK High 4 4 ns
t
HTAP
TDI, TMS Hold After TCK High 4 4 ns
t
SSYS
System Inputs Setup Before TCK High
1
12 12 ns
t
HSYS
System Inputs Hold After TCK High
1
55ns
t
TRSTW
TRST Pulse Width
2
(measured in TCK cycles) 4 4 TCK
Switching Characteristics
t
DTDO
TDO Delay from TCK Low 10 10 ns
t
DSYS
System Outputs Delay After TCK Low
3
12 12 ns
1
System Inputs = DATA15–0, ARDY, SCL, SDA, PF15–0, PG15–0, PH15–0, RESET, NMI, BMODE3–0.
2
50 MHz Maximum.
3
System Outputs = DATA15–0, ADDR19–1, ABE1–0, AOE, ARE, AWE, AMS3–0, SRAS, SCAS, SWE, SCKE, CLKOUT, SA10, SMS, SCL, SDA, PF15–0, PG15–0, PH15–0.
Figure 42. JTAG Port Timing
TCK
TMS
TDI
TDO
SYSTEM
INPUTS
SYSTEM
OUTPUTS
t
TCK
t
STAP
t
HTAP
t
DTDO
t
SSYS
t
HSYS
t
DSYS