Datasheet

Rev. D | Page 70 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 62. 10/100 Ethernet MAC Controller Timing: MII/RMII Asynchronous Signal
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
ECOLH
COL Pulse Width High
1
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
t
ECOLL
COL Pulse Width Low
1
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
t
ETxCLK
× 1.5
t
ERxCLK
× 1.5
ns
t
ECRSH
CRS Pulse Width High
2
t
ETxCLK
× 1.5 t
ETxCLK
× 1.5 ns
t
ECRSL
CRS Pulse Width Low
2
t
ETxCLK
× 1.5 t
ETxCLK
× 1.5 ns
1
MII/RMII asynchronous signals are COL and CRS. These signals are applicable in both MII and RMII modes. The asynchronous COL input is synchronized separately to
both the ETxCLK and the ERxCLK, and the COL input must have a minimum pulse width high or low at least 1.5 times the period of the slower of the two clocks.
2
The asynchronous CRS input is synchronized to the ETxCLK, and the CRS input must have a minimum pulse width high or low at least 1.5 times the period of ETxCLK.
Figure 40. 10/100 Ethernet MAC Controller Timing: Asynchronous Signal
Table 63. 10/100 Ethernet MAC Controller Timing: MII Station Management
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
1
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
MDIOS
MDIO Input Valid to MDC Rising Edge
(Setup)
11.5 11.5 10 10 ns
t
MDCIH
MDC Rising Edge to MDIO Input Invalid
(Hold)
11.5 11.5 10 10 ns
Switching Characteristics
t
MDCOV
MDC Falling Edge to MDIO Output Valid 25 25 25 25 ns
t
MDCOH
MDC Falling Edge to MDIO Output
Invalid (Hold)
–1 –1 –1 –1 ns
1
MDC/MDIO is a 2-wire serial bidirectional port for controlling one or more external PHYs. MDC is an output clock whose minimum period is programmable as a multiple
of the system clock SCLK. MDIO is a bidirectional data line.
MIICRS, COL
t
ECRSH
t
ECOLH
t
ECRSL
t
ECOLL