Datasheet

Rev. D | Page 7 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
controller to prioritize and control all system events. Conceptu-
ally, interrupts from the peripherals enter into the SIC and are
then routed directly into the general-purpose interrupts of the
CEC.
Core Event Controller (CEC)
The CEC supports nine general-purpose interrupts (IVG15–7),
in addition to the dedicated interrupt and exception events. Of
these general-purpose interrupts, the two lowest-priority
interrupts (IVG15–14) are recommended to be reserved for
software interrupt handlers, leaving seven prioritized interrupt
inputs to support the peripherals of the processor. Table 2
describes the inputs to the CEC, identifies their names in the
event vector table (EVT), and lists their priorities.
System Interrupt Controller (SIC)
The system interrupt controller provides the mapping and rout-
ing of events from the many peripheral interrupt sources to the
prioritized general-purpose interrupt inputs of the CEC.
Although the processor provides a default mapping, the user
can alter the mappings and priorities of interrupt events by writ-
ing the appropriate values into the interrupt assignment
registers (SIC_IARx). Table 3 describes the inputs into the SIC
and the default mappings into the CEC.
Table 2. Core Event Controller (CEC)
Priority
(0 is Highest) Event Class EVT Entry
0Emulation/Test ControlEMU
1RESET
RST
2 Nonmaskable Interrupt NMI
3Exception EVX
4 Reserved —
5 Hardware Error IVHW
6 Core Timer IVTMR
7 General-Purpose Interrupt 7 IVG7
8 General-Purpose Interrupt 8 IVG8
9 General-Purpose Interrupt 9 IVG9
10 General-Purpose Interrupt 10 IVG10
11 General-Purpose Interrupt 11 IVG11
12 General-Purpose Interrupt 12 IVG12
13 General-Purpose Interrupt 13 IVG13
14 General-Purpose Interrupt 14 IVG14
15 General-Purpose Interrupt 15 IVG15
Table 3. System Interrupt Controller (SIC)
Peripheral Interrupt Event
General Purpose
Interrupt (at RESET)Peripheral Interrupt ID
Default
Core Interrupt ID
SIC Registers
PLL Wakeup Interrupt IVG7 0 0 IAR0 IMASK0, ISR0, IWR0
DMA Error 0 (generic) IVG7 1 0 IAR0 IMASK0, ISR0, IWR0
DMAR0 Block Interrupt IVG7 2 0 IAR0 IMASK0, ISR0, IWR0
DMAR1 Block Interrupt IVG7 3 0 IAR0 IMASK0, ISR0, IWR0
DMAR0 Overflow Error IVG7 4 0 IAR0 IMASK0, ISR0, IWR0
DMAR1 Overflow Error IVG7 5 0 IAR0 IMASK0, ISR0, IWR0
PPI Error IVG7 6 0 IAR0 IMASK0, ISR0, IWR0
MAC Status IVG7 7 0 IAR0 IMASK0, ISR0, IWR0
SPORT0 Status IVG7 8 0 IAR1 IMASK0, ISR0, IWR0
SPORT1 Status IVG7 9 0 IAR1 IMASK0, ISR0, IWR0
Reserved IVG7 10 0 IAR1 IMASK0, ISR0, IWR0
Reserved IVG7 11 0 IAR1 IMASK0, ISR0, IWR0
UART0 Status IVG7 12 0 IAR1 IMASK0, ISR0, IWR0
UART1 Status IVG7 13 0 IAR1 IMASK0, ISR0, IWR0
RTC IVG8 14 1 IAR1 IMASK0, ISR0, IWR0
DMA Channel 0 (PPI/NFC) IVG8 15 1 IAR1 IMASK0, ISR0, IWR0
DMA Channel 3 (SPORT0 RX) IVG9 16 2 IAR2 IMASK0, ISR0, IWR0
DMA Channel 4 (SPORT0 TX) IVG9 17 2 IAR2 IMASK0, ISR0, IWR0
DMA Channel 5 (SPORT1 RX) IVG9 18 2 IAR2 IMASK0, ISR0, IWR0
DMA Channel 6 (SPORT1 TX) IVG9 19 2 IAR2 IMASK0, ISR0, IWR0
TWI IVG10 20 3 IAR2 IMASK0, ISR0, IWR0
DMA Channel 7 (SPI) IVG10 21 3 IAR2 IMASK0, ISR0, IWR0
DMA Channel 8 (UART0 RX) IVG10 22 3 IAR2 IMASK0, ISR0, IWR0
DMA Channel 9 (UART0 TX) IVG10 23 3 IAR2 IMASK0, ISR0, IWR0
DMA Channel 10 (UART1 RX) IVG10 24 3 IAR3 IMASK0, ISR0, IWR0
DMA Channel 11 (UART1 TX) IVG10 25 3 IAR3 IMASK0, ISR0, IWR0