Datasheet

Rev. D | Page 69 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 60. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Parameter
1
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
EREFCLKF
REF_CLK Frequency (f
SCLK
= SCLK Frequency) None 50 + 1% None 50 + 1% MHz
t
EREFCLKW
EREF_CLK Width (t
EREFCLK
= EREFCLK Period) t
EREFCLK
× 40% t
EREFCLK
× 60% t
EREFCLK
× 35% t
EREFCLK
× 65% ns
t
EREFCLKIS
Rx Input Valid to RMII REF_CLK Rising Edge (Data In
Setup)
44ns
t
EREFCLKIH
RMII REF_CLK Rising Edge to Rx Input Invalid (Data In
Hold)
22ns
1
RMII inputs synchronous to RMII REF_CLK are ERxD1–0, RMII CRS_DV, and ERxER.
Figure 38. 10/100 Ethernet MAC Controller Timing: RMII Receive Signal
Table 61. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
1
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Switching Characteristics
t
EREFCLKOV
RMII REF_CLK Rising Edge
to Tx Output Valid (Data Out Valid)
8.1 8.1 7.5 7.5 ns
t
EREFCLKOH
RMII REF_CLK Rising Edge
to Tx Output Invalid (Data Out Hold)
22 22 ns
1
RMII outputs synchronous to RMII REF_CLK are ETxD1–0.
Figure 39. 10/100 Ethernet MAC Controller Timing: RMII Transmit Signal
t
REFCLKIS
t
REFCLKIH
ERxD1–0
ERxDV
ERxER
RMII_REF_CLK
t
REFCLKW
t
REFCLK
t
REFCLKOV
t
REFCLKOH
RMII_REF_CLK
ETxD1–0
ETxEN
t
REFCLK