Datasheet

Rev. D | Page 68 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
10/100 Ethernet MAC Controller Timing
Table 58 through Table 63 and Figure 36 through Figure 41
describe the 10/100 Ethernet MAC Controller operations.
Table 58. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Parameter
1
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
ERXCLKF
ERxCLK Frequency (f
SCLK
= SCLK Frequency) None 25 + 1% None 25 + 1% MHz
t
ERXCLKW
ERxCLK Width (t
ERxCLK
= ERxCLK Period) t
ERxCLK
× 40% t
ERxCLK
× 60% t
ERxCLK
× 35% t
ERxCLK
× 65% ns
t
ERXCLKIS
Rx Input Valid to ERxCLK Rising Edge (Data In Setup) 7.5 7.5 ns
t
ERXCLKIH
ERxCLK Rising Edge to Rx Input Invalid (Data In Hold) 7.5 7.5 ns
1
MII inputs synchronous to ERxCLK are ERxD3–0, ERxDV, and ERxER.
Figure 36. 10/100 Ethernet MAC Controller Timing: MII Receive Signal
Table 59. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
Parameter
1
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Switching Characteristics
t
ETXCLKF
ETxCLK Frequency (f
SCLK
= SCLK Frequency) None 25 + 1% None 25 + 1% MHz
t
ETXCLKW
ETxCLK Width (t
ETxCLK
= ETxCLK Period) t
ETxCLK
× 40% t
ETxCLK
× 60% t
ETxCLK
× 35% t
ETxCLK
× 65% ns
t
ETXCLKOV
ETxCLK Rising Edge to Tx Output Valid (Data Out Valid) 20 20 ns
t
ETXCLKOH
ETxCLK Rising Edge to Tx Output Invalid (Data Out
Hold)
00ns
1
MII outputs synchronous to ETxCLK are ETxD3–0.
Figure 37. 10/100 Ethernet MAC Controller Timing: MII Transmit Signal
t
ERXCLKIS
t
ERXCLKIH
ERxD3–0
ERxDV
ERxER
ERx_CLK
t
ERXCLKW
t
ERXCLK
t
ETXCLKOH
ETxD3–0
ETxEN
MIITxCLK
t
ETXCLK
t
ETXCLKOV
t
ETXCLKW