Datasheet

Rev. D | Page 66 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
HOSTDP A/C Timing- Host Write Cycle
Table 57 describes the HOSTDP A/C Host Write Cycle timing
requirements.
Table 57. Host Write Cycle Timing Requirements
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SADWRL
HOST_ADDR/HOST_CE Setup
before HOST_WR falling edge
4444ns
t
HADWRH
HOST_ADDR/HOST_CE Hold
after HOST_WR rising edge
2.5 2.5 2.5 2.5 ns
t
WRWL
HOST_WR pulse width low
(ACK mode)
t
DRDYWRL
+
t
RDYPRD
+
t
DWRHRDY
t
DRDYWRL
+
t
RDYPRD
+
t
DWRHRDY
t
DRDYWRL
+
t
RDYPRD
+
t
DWRHRDY
t
DRDYWRL
+
t
RDYPRD
+
t
DWRHRDY
ns
HOST_WR pulse width low
(INT mode)
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
ns
t
WRWH
HOST_WR pulse width high
or time between HOST_WR
rising edge and HOST_RD
falling edge
2 × t
SCLK
2 × t
SCLK
2 × t
SCLK
2 × t
SCLK
ns
t
DWRHRDY
HOST_WR rising edge delay
after HOST_ACK rising edge
(ACK mode)
2.02.000ns
t
HDATWH
Data Hold after HOST_WR rising edge 2.5 2.5 2.5 2.5 ns
t
SDATWH
Data Setup before HOST_WR
rising edge
3.5 2.5 2.5 2.5 ns
Switching Characteristics
t
DRDYWRL
HOST_ACK falling edge after HOST_CE
asserted (ACK mode)
12.5 11.5 11.5 11.5 ns
t
RDYPWR
HOST_ACK low pulse-width for Write
access (ACK mode)
NM
1
NM
1
NM
1
NM
1
ns
1
NM (Not Measured) — This parameter is based on t
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO
status and is system design dependent.