Datasheet

Rev. D | Page 64 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
HOSTDP A/C Timing- Host Read Cycle
Table 56 describes the HOSTDP A/C Host Read Cycle timing
requirements.
Table 56. Host Read Cycle Timing Requirements
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SADRDL
HOST_ADDR and HOST_CE Setup
before HOST_RD falling edge
4444ns
t
HADRDH
HOST_ADDR and HOST_CE Hold
after HOST_RD rising edge
2.5 2.5 2.5 2.5 ns
t
RDWL
HOST_RD pulse width low
(ACK mode)
t
DRDYRDL
+
t
RDYPRD
+
t
DRDHRDY
t
DRDYRDL
+
t
RDYPRD
+
t
DRDHRDY
t
DRDYRDL
+
t
RDYPRD
+
t
DRDHRDY
t
DRDYRDL
+
t
RDYPRD
+
t
DRDHRDY
ns
t
RDWL
HOST_RD pulse width low
(INT mode)
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
1.5 × t
SCLK
+ 8.7
ns
t
RDWH
HOST_RD pulse width high or time
between HOST_RD
rising edge and
HOST_WR falling edge
2 × t
SCLK
2 × t
SCLK
2 × t
SCLK
2 × t
SCLK
ns
t
DRDHRDY
HOST_RD rising edge delay after
HOST_ACK rising edge (ACK mode)
2.02.000ns
Switching Characteristics
t
SDATRDY
Data valid prior HOST_ACK rising
edge (ACK mode)
4.5 3.5 4.5 3.5 ns
t
DRDYRDL
Host_ACK falling edge after
HOST_CE (ACK mode)
12.5 11.25 11.25 11.25 ns
t
RDYPRD
HOST_ACK low pulse-width for
Read access (ACK mode)
NM
1
NM
1
NM
1
NM
1
ns
t
DDARWH
Data disable after HOST_RD 11.0 9.0 9.0 9.0 ns
t
ACC
Data valid after HOST_RD falling
edge (INT mode)
1.5 × t
SCLK
1.5 × t
SCLK
1.5 × t
SCLK
1.5 × t
SCLK
ns
t
HDARWH
Data hold after HOST_RD rising
edge
1.0 1.0 1.0 1.0 ns
1
NM (Not Measured) — This parameter is based on t
SCLK
. It is not measured because the number of SCLK cycles for which HOST_ACK is low depends on the Host DMA FIFO
status and is system design dependent.