Datasheet

Rev. D | Page 63 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Timer Clock Timing
Table 54 and Figure 32 describe timer clock timing.
Up/Down Counter/Rotary Encoder Timing
Table 54. Timer Clock Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Switching Characteristic
t
TODP
Timer Output Update Delay After PPI_CLK High 12.0 12.0 ns
Figure 32. Timer Clock Timing
Table 55. Up/Down Counter/Rotary Encoder Timing
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
WCOUNT
Up/Down Counter/Rotary Encoder Input Pulse Width t
SCLK
+ 1 t
SCLK
+ 1 ns
t
CIS
Counter Input Setup Time Before CLKOUT High
1
1
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize counter inputs.
9.0 7.0 ns
t
CIH
Counter Input Hold Time After CLKOUT High
1
00ns
Figure 33. Up/Down Counter/Rotary Encoder Timing
PPI_CLK
TMRx OUTPUT
t
TODP
CLKOUT
CUD/CDG/CZM
t
CIS
t
CIH
t
WCOUNT