Datasheet

Rev. D | Page 62 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Timer Cycle Timing
Table 53 and Figure 31 describe timer expired operations. The
input signal is asynchronous in “width capture mode” and
“external clock mode” and has an absolute maximum input fre-
quency of (f
SCLK
/2) MHz.
Table 53. Timer Cycle Timing
ADSP-BF522/ADSP-BF524/ADSP-BF526 ADSP-BF523/ADSP-BF525/ADSP-BF527
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
MinMaxMinMaxMinMaxMinMaxUnit
Timing Requirements
t
WL
Timer Pulse Width Input
Low (Measured In SCLK
Cycles)
1
t
SCLK
t
SCLK
t
SCLK
t
SCLK
ns
t
WH
Timer Pulse Width Input
High (Measured In SCLK
Cycles)
1
t
SCLK
t
SCLK
t
SCLK
t
SCLK
ns
t
TIS
Timer Input Setup Time
Before CLKOUT Low
2
10 7 8.1 6.2 ns
t
TIH
Timer Input Hold Time
After CLKOUT Low
2
–2 –2 –2 –2 ns
Switching Characteristics
t
HTO
Timer Pulse Width Output
(Measured In SCLK Cycles)
t
SCLK
–1.5 (2
32
– 1)t
SCLK
t
SCLK
– 1 (2
32
– 1)t
SCLK
t
SCLK
– 1 (2
32
– 1)t
SCLK
t
SCLK
– 1 (2
32
– 1)t
SCLK
ns
t
TOD
Timer Output Update
Delay After CLKOUT High
6666ns
1
The minimum pulse widths apply for TMRx signals in width capture and external clock modes. They also apply to the PF15 or PPI_CLK signals in PWM output mode.
2
Either a valid setup and hold time or a valid pulse width is sufficient. There is no need to resynchronize programmable flag inputs.
Figure 31. Timer Cycle Timing
CLKOUT
TMRx OUTPUT
TMRx INPUT
t
TIS
t
TIH
t
WH
,t
WL
t
TOD
t
HTO