Datasheet

Rev. D | Page 58 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Serial Peripheral Interface (SPI) Port—Master Timing
Table 48 and Figure 28 describe SPI port master operations.
Table 48. Serial Peripheral Interface (SPI) Port—Master Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SSPIDM
Data Input Valid to SCK Edge (Data
Input Setup)
11.6 9.6 11.6 9.6 ns
t
HSPIDM
SCK Sampling Edge to Data Input
Invalid
–1.5 –1.5 –1.5 –1.5 ns
Switching Characteristics
t
SDSCIM
SPISELx low to First SCK Edge 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICHM
Serial Clock High Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLM
Serial Clock Low Period 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPICLK
Serial Clock Period 4 × t
SCLK
–1.5 4 × t
SCLK
–1.5 4 × t
SCLK
–1.5 4 × t
SCLK
–1.5 ns
t
HDSM
Last SCK Edge to SPISELx High 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
SPITDM
Sequential Transfer Delay 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 2 × t
SCLK
–1.5 ns
t
DDSPIDM
SCK Edge to Data Out Valid (Data
Out Delay)
6666ns
t
HDSPIDM
SCK Edge to Data Out Invalid (Data
Out Hold)
–1.0 –1.0 –1.0 –1.0 ns
Figure 28. Serial Peripheral Interface (SPI) Port—Master Timing
t
SDSCIM
t
SPICLK
t
HDSM
t
SPITDM
t
SPICLM
t
SPICHM
t
HDSPIDM
t
HSPIDM
t
SSPIDM
SPIxSELy
(OUTPUT)
SPIxSCK
(OUTPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
SPIxMOSI
(OUTPUT)
SPIxMISO
(INPUT)
CPHA = 1
CPHA = 0
t
DDSPIDM
t
HSPIDM
t
SSPIDM
t
HDSPIDM
t
DDSPIDM