Datasheet

Rev. D | Page 55 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Figure 24. Serial Ports
Figure 25. Serial Port Start Up with External Clock and Frame Sync
t
SDRI
RSCLKx
DRx
DRIVE EDGE
t
HDRI
t
SFSI
t
HFSI
t
DFSI
t
H
OFSI
t
SCLKIW
DATA RECEIVE—INTERNAL CLOCK
t
SDRE
DATA RECEIVE—EXTERNAL CLOCK
RSCLKx
DRx
t
HDRE
t
SFSE
t
HFSE
t
DFSE
t
SCLKEW
t
HOFSE
t
DDTI
t
HDTI
TSCLKx
TFSx
(INPUT)
DTx
t
SFSI
t
HFSI
t
SCLKIW
t
DFSI
t
HOFSI
DATA TRANSMIT—INTERNAL CLOCK
t
DDTE
t
HDTE
TSCLKx
DTx
t
SFSE
t
DFSE
t
SCLKEW
t
HOFSE
DATA TRANSMIT—EXTERNAL CLOCK
SAMPLE EDGE
DRIVE EDGE SAMPLE EDGE DRIVE EDGE SAMPLE EDGE
DRIVE EDGE SAMPLE EDGE
t
SCLKE
t
SCLKE
t
HFSE
TFSx
(OUTPUT)
TFSx
(INPUT)
TFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
RFSx
(INPUT)
RFSx
(OUTPUT)
TSCLKx
(INPUT)
TFSx
(INPUT)
RFSx
(INPUT)
RSCLKx
(INPUT)
t
SUDTE
t
SUDRE
FIRST
TSCLKx/RSCLKx
EDGE AFTER
SPORT ENABLED