Datasheet

Rev. D | Page 54 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 44. Serial Ports—Internal Clock for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0 9.6 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–1.5 –1.5 ns
t
SDRI
Receive Data Setup Before RSCLKx
1
11.0 9.6 ns
t
HDRI
Receive Data Hold After RSCLKx
1
–1.5 –1.5 ns
Switching Characteristics
t
SCLKIW
TSCLKx/RSCLKx Width 10.0 8.0 ns
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
3.0 3.0 ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx (Internally Generated TFSx/RFSx)
2
–2.0 –1.0 ns
t
DDTI
Transmit Data Delay After TSCLKx
2
3.0 3.0 ns
t
HDTI
Transmit Data Hold After TSCLKx
2
–1.8 –1.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.
Table 45. Serial Ports—Internal Clock for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SFSI
TFSx/RFSx Setup Before TSCLKx/RSCLKx
1
11.0 9.6 ns
t
HFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
–1.5 –1.5 ns
t
SDRI
Receive Data Setup Before RSCLKx
1
11.0 9.6 ns
t
HDRI
Receive Data Hold After RSCLKx
1
–1.5 –1.5 ns
Switching Characteristics
t
SCLKIW
TSCLKx/RSCLKx Width 4.5 4.5 ns
t
DFSI
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
2
3.0 3.0 ns
t
HOFSI
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
2
–1.0 –1.0 ns
t
DDTI
Transmit Data Delay After TSCLKx
2
3.0 3.0 ns
t
HDTI
Transmit Data Hold After TSCLKx
2
–1.8 –1.5 ns
1
Referenced to sample edge.
2
Referenced to drive edge.