Datasheet

Rev. D | Page 53 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Serial Ports
Table 43 through Table 47 on Page 57 and Figure 24 on Page 55
through Figure 27 on Page 57 describe serial port operations.
Table 43. Serial Ports—External Clock
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SFSE
TFSx/RFSx Setup Before TSCLKx RSCLKx
1
3.0 3.0 3.0 3.0 ns
t
HFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
1
3.0 3.0 3.0 3.0 ns
t
SDRE
Receive Data Setup Before RSCLKx
1
3.0 3.0 3.0 3.0 ns
t
HDRE
Receive Data Hold After RSCLKx
1
3.5 3.0 3.5 3.0 ns
t
SCLKEW
TSCLKx/RSCLKx Width 7.0 4.5 7.0 4.5 ns
t
SCLKE
TSCLKx/RSCLKx Period 2.0 × t
SCLK
2.0 × t
SCLK
2.0 × t
SCLK
2.0 × t
SCLK
ns
t
SUDTE
Start-Up Delay From SPORT Enable To
First External TFSx
2
4.0 × t
SCLKE
4.0 × t
SCLKE
4.0 × t
SCLKE
4.0 × t
SCLKE
ns
t
SUDRE
Start-Up Delay From SPORT Enable To
First External RFSx
2
4.0 × t
SCLKE
4.0 × t
SCLKE
4.0 × t
SCLKE
4.0 × t
SCLKE
ns
Switching Characteristics
t
DFSE
TFSx/RFSx Delay After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
10.0 10.0 10.0 10.0 ns
t
HOFSE
TFSx/RFSx Hold After TSCLKx/RSCLKx
(Internally Generated TFSx/RFSx)
3
0.0 0.0 0.0 0.0 ns
t
DDTE
Transmit Data Delay After TSCLKx
3
10.0 10.0 10.0 10.0 ns
t
HDTE
Transmit Data Hold After TSCLKx
3
0.0 0.0 0.0 0.0 ns
1
Referenced to sample edge.
2
Verified in design but untested.
3
Referenced to drive edge.