Datasheet

Rev. D | Page 50 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Parallel Peripheral Interface Timing
Table 41 and Figure 20 on Page 51, Figure 24 on Page 55, and
Figure 27 on Page 57 describe parallel peripheral interface
operations.
Table 41. Parallel Peripheral Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width
1
6.4 6.4 ns
t
PCLK
PPI_CLK Period
1
25.0 20.0 ns
Timing Requirements - GP Input and Frame Capture Modes
t
SFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.7 6.7 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.2 1.2 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 4.1 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 2.0 1.6 ns
Switching Characteristics - GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 8.0 8.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 8.2 8.0 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 2.3 1.9 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.
Table 42. Parallel Peripheral Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
V
DDEXT
1.8V Nominal
V
DDEXT
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
PCLKW
PPI_CLK Width
1
6.0 6.0 ns
t
PCLK
PPI_CLK Period
1
20.0 15.0 ns
Timing Requirements - GP Input and Frame Capture Modes
t
SFSPE
External Frame Sync Setup Before PPI_CLK
(Nonsampling Edge for Rx, Sampling Edge for Tx)
6.7 6.7 ns
t
HFSPE
External Frame Sync Hold After PPI_CLK 1.0 1.0 ns
t
SDRPE
Receive Data Setup Before PPI_CLK 3.5 3.5 ns
t
HDRPE
Receive Data Hold After PPI_CLK 2.0 1.6 ns
Switching Characteristics - GP Output and Frame Capture Modes
t
DFSPE
Internal Frame Sync Delay After PPI_CLK 8.0 8.0 ns
t
HOFSPE
Internal Frame Sync Hold After PPI_CLK 1.7 1.7 ns
t
DDTPE
Transmit Data Delay After PPI_CLK 8.0 8.0 ns
t
HDTPE
Transmit Data Hold After PPI_CLK 2.3 1.9 ns
1
PPI_CLK frequency cannot exceed f
SCLK
/2.