Datasheet

Rev. D | Page 49 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
External DMA Request Timing
Table 39, Table 40, and Figure 19 describe the External DMA
Request operations.
Table 39. External DMA Request Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
1
Parameter
V
DDEXT
/V
DDMEM
1.8 V Nominal
V
DDEXT
/V
DDMEM
2.5 V or 3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
DS
DMARx Asserted to CLKOUT High Setup 9.0 6.0 ns
t
DH
CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns
t
DMARACT
DMARx Active Pulse Width 1.0 × t
SCLK
1.0 × t
SCLK
ns
t
DMARINACT
DMARx Inactive Pulse Width 1.75 × t
SCLK
1.75 × t
SCLK
ns
1
Because the external DMA control pins are part of the V
DDEXT
power domain and the CLKOUT signal is part of the V
DDMEM
power domain, systems in which V
DDEXT
and
V
DDMEM
are NOT equal may require level shifting logic for correct operation.
Table 40. External DMA Request Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
1
Parameter
V
DDEXT
/V
DDMEM
1.8 V Nominal
V
DDEXT
/V
DDMEM
2.5 V or 3.3 V Nominal
Min Max Min Max Unit
Timing Requirements
t
DS
DMARx Asserted to CLKOUT High Setup 8.0 6.0 ns
t
DH
CLKOUT High to DMARx Deasserted Hold Time 0.0 0.0 ns
t
DMARACT
DMARx Active Pulse Width 1.0 × t
SCLK
1.0 × t
SCLK
ns
t
DMARINACT
DMARx Inactive Pulse Width 1.75 × t
SCLK
1.75 × t
SCLK
ns
1
Because the external DMA control pins are part of the V
DDEXT
power domain and the CLKOUT signal is part of the V
DDMEM
power domain, systems in which V
DDEXT
and
V
DDMEM
are NOT equal may require level shifting logic for correct operation.
Figure 19. External DMA Request Timing
CLKOUT
t
DS
DMAR0/1
(ACTIVE LOW)
DMAR0/1
(ACTIVE HIGH)
t
DMARACT
t
DMARINACT
t
DH