Datasheet

Rev. D | Page 47 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
SDRAM Interface Timing
Table 37. SDRAM Interface Timing for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
V
DDMEM
1.8V Nominal
V
DDMEM
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SSDAT
Data Setup Before CLKOUT 1.5 1.5 ns
t
HSDAT
Data Hold After CLKOUT 1.3 0.8 ns
Switching Characteristics
t
SCLK
CLKOUT Period
1
1
The t
SCLK
value is the inverse of the f
SCLK
specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.
12.5 10 ns
t
SCLKH
CLKOUT Width High 5.0 4.0 ns
t
SCLKL
CLKOUT Width Low 5.0 4.0 ns
t
DCAD
Command, Address, Data Delay After CLKOUT
2
2
Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
5.0 4.0 ns
t
HCAD
Command, Address, Data Hold After CLKOUT
2
1.0 1.0 ns
t
DSDAT
Data Disable After CLKOUT 5.5 5.0 ns
t
ENSDAT
Data Enable After CLKOUT 0.0 0.0 ns
Table 38. SDRAM Interface Timing for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter
V
DDMEM
1.8V Nominal
V
DDMEM
2.5 V or 3.3V Nominal
Min Max Min Max Unit
Timing Requirements
t
SSDAT
Data Setup Before CLKOUT 1.5 1.5 ns
t
HSDAT
Data Hold After CLKOUT 1.0 0.8 ns
Switching Characteristics
t
SCLK
CLKOUT Period
1
1
The t
SCLK
value is the inverse of the f
SCLK
specification discussed in Table 14 and Table 17. Package type and reduced supply voltages affect the best-case values listed here.
10 7.5 ns
t
SCLKH
CLKOUT Width High 2.5 2.5 ns
t
SCLKL
CLKOUT Width Low 2.5 2.5 ns
t
DCAD
Command, Address, Data Delay After CLKOUT
2
2
Command balls include: SRAS, SCAS, SWE, SDQM, SMS, SA10, SCKE.
4.0 4.0 ns
t
HCAD
Command, Address, Data Hold After CLKOUT
2
1.0 1.0 ns
t
DSDAT
Data Disable After CLKOUT 5.0 4.0 ns
t
ENSDAT
Data Enable After CLKOUT 0.0 0.0 ns