Datasheet

Rev. D | Page 44 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
In Figure 13, ND_DATA is ND_D0–D7.
Figure 13. NAND Flash Controller Interface Timing — Command Write Cycle
t
CLEWL
t
ALEWL
ND_DATA
t
CH
t
CWL
t
CLH
t
ALH
t
DWH
ND_CE
ND_CLE
ND_ALE
AWE
t
WP
t
DWS
In Figure 14, ND_DATA is ND_D0–D7.
Figure 14. NAND Flash Controller Interface Timing — Address Write Cycle
ND_DATA
t
WP
t
WP
t
ALH
t
ALH
ND_CE
ND_CLE
ND_ALE
AWE
t
CWL
t
CLEWL
t
ALEWL
t
WHWL
t
WC
t
DWS
t
DWH
t
DWS
t
DWH
t
ALEWL