Datasheet

Rev. D | Page 43 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
NAND Flash Controller Interface Timing
Table 36 and Figure 13 on Page 44 through Figure 17 on
Page 46 describe NAND Flash Controller Interface operations.
Table 36. NAND Flash Controller Interface Timing
V
DDEXT
1.8 V Nominal
V
DDEXT
2.5 V or 3.3 V Nominal
Parameter Min Min Unit
Write Cycle
Switching Characteristics
t
CWL
ND_CE Setup Time to AWE Low 1.0 × t
SCLK
– 4 1.0 × t
SCLK
– 4 ns
t
CH
ND_CE Hold Time From AWE High 3.0 × t
SCLK
– 4 3.0 × t
SCLK
– 4 ns
t
CLEWL
ND_CLE Setup Time to AWE Low 0.0 0.0 ns
t
CLH
ND_CLE Hold Time From AWE high 2.5 × t
SCLK
– 4 2.5 × t
SCLK
– 4 ns
t
ALEWL
ND_ALE Setup Time to AWE Low 0.0 0.0 ns
t
ALH
ND_ALE Hold Time From AWE High 2.5 × t
SCLK
– 4 2.5 × t
SCLK
– 4 ns
t
WP
1
AWE Low to AWE high (WR_DLY +1.0) × t
SCLK
– 4 (WR_DLY +1.0) × t
SCLK
– 4 ns
t
WHWL
AWE High to AWE Low 4.0 × t
SCLK
– 4 4.0 × t
SCLK
– 4 ns
t
WC
1
AWE Low to AWE Low (WR_DLY +5.0) × t
SCLK
– 4 (WR_DLY +5.0) × t
SCLK
– 4 ns
t
DWS
1
Data Setup Time for a Write Access (WR_DLY +1.5) × t
SCLK
– 4 (WR_DLY +1.5) × t
SCLK
– 4 ns
t
DWH
Data Hold Time for a Write Access 2.5 × t
SCLK
– 4 2.5 × t
SCLK
– 4 ns
Read Cycle
Switching Characteristics
t
CRL
ND_CE Setup Time to ARE Low 1.0 × t
SCLK
– 4 1.0 × t
SCLK
– 4 ns
t
CRH
ND_CE Hold Time From ARE High 3.0 × t
SCLK
– 4 3.0 × t
SCLK
– 4 ns
t
RP
1
ARE Low to ARE High (RD_DLY +1.0) × t
SCLK
– 4 (RD_DLY +1.0) × t
SCLK
– 4 ns
t
RHRL
ARE High to ARE Low 4.0 × t
SCLK
– 4 4.0 × t
SCLK
– 4 ns
t
RC
1
ARE Low to ARE Low (RD_DLY +5.0) × t
SCLK
– 4 (RD_DLY +5.0) × t
SCLK
– 4 ns
Timing Requirements (ADSP-BF522/ADSP-BF524/ADSP-BF526)
t
DRS
Data Setup Time for a Read Transaction 14.0 10.0 ns
t
DRH
Data Hold Time for a Read Transaction 0.0 0.0 ns
Timing Requirements (ADSP-BF523/ADSP-BF525/ADSP-BF527)
t
DRS
Data Setup Time for a Read Transaction 11.0 8.0 ns
t
DRH
Data Hold Time for a Read Transaction 0.0 0.0 ns
Write Followed by Read
Switching Characteristic
t
WHRL
AWE High to ARE Low 5.0 × t
SCLK
– 4 5.0 × t
SCLK
– 4 ns
1
WR_DLY and RD_DLY are defined in the NFC_CTL register.