Datasheet

Rev. D | Page 42 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Asynchronous Memory Write Cycle Timing
Table 35. Asynchronous Memory Write Cycle Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDMEM
1.8 V Nominal
V
DDMEM
2.5 V or 3.3 V
Nominal
V
DDMEM
1.8 V Nominal
V
DDMEM
2.5 V or 3.3 V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SARDY
ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 0.2 0.2 0.2 0.2 ns
Switching Characteristics
t
DDAT
DATA15–0 Disable After CLKOUT 6.0 6.0 6.0 6.0 ns
t
ENDAT
DATA15–0 Enable After CLKOUT 0.0 0.0 0.0 0.0 ns
t
DO
Output Delay After CLKOUT
1
1
Output balls include AMS3–0, ABE1–0, ADDR19–1, DATA15– 0, AWE.
6.0 6.0 6.0 6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 0.8 0.8 0.8 ns
Figure 12. Asynchronous Memory Write Cycle Timing
SETUP
2 CYCLES
PROGRAMMED
WRITE
ACCESS
2 CYCLES
ACCESS
EXTEND
1 CYCLE
HOLD
1 CYCLE
t
DO
t
HO
CLKOUT
AMSx
ABE1–0
ADDR19–1
AWE
ARDY
DATA 15–0
t
SARDY
t
SARDY
t
DDAT
t
ENDAT
t
HARDY
t
HO
t
DO
t
HARDY