Datasheet

Rev. D | Page 41 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Asynchronous Memory Read Cycle Timing
Table 34. Asynchronous Memory Read Cycle Timing
ADSP-BF522/ADSP-BF524/
ADSP-BF526
ADSP-BF523/ADSP-BF525/
ADSP-BF527
Parameter
V
DDMEM
1.8 V Nominal
V
DDMEM
2.5 V or 3.3 V
Nominal
V
DDMEM
1.8 V Nominal
V
DDMEM
2.5 V or 3.3 V
Nominal
Min Max Min Max Min Max Min Max Unit
Timing Requirements
t
SDAT
DATA15–0 Setup Before CLKOUT 2.1 2.1 2.1 2.1 ns
t
HDAT
DATA15–0 Hold After CLKOUT 1.2 0.8 0.9 0.8 ns
t
SARDY
ARDY Setup Before CLKOUT 4.0 4.0 4.0 4.0 ns
t
HARDY
ARDY Hold After CLKOUT 0.2 0.2 0.2 0.2 ns
Switching Characteristics
t
DO
Output Delay After CLKOUT
1
1
Output balls include AMS3–0, ABE1–0, ADDR19–1, AOE, ARE.
6.0 6.0 6.0 6.0 ns
t
HO
Output Hold After CLKOUT
1
0.8 0.8 0.8 0.8 ns
Figure 11. Asynchronous Memory Read Cycle Timing
t
HARDY
SETUP
2 CYCLES
PROGRAMMED READ
ACCESS 4 CYCLES
ACCESS EXTENDED
3 CYCLES
HOLD
1 CYCLE
t
DO
t
HO
t
DO
t
HARDY
t
SARDY
t
SDAT
t
HDAT
t
SARDY
CLKOUT
AMSx
ABE1–0
ADDR19–1
AOE
ARE
ARDY
DATA 15–0
t
HO