Datasheet

Rev. D | Page 31 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Clock Related Operating Conditions
for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Table 15 describes the core clock timing requirements for the
ADSP-BF523/ADSP-BF525/ADSP-BF527 processors. Take care
in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock (see Table 17). Table 16
describes phase-locked loop operating conditions.
Use the nominal voltage setting (Table 15) for internal and
external regulators.
Table 15. Core Clock (CCLK) Requirements (All Instruction Rates
1
) for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter Nominal Voltage Setting Max Unit
f
CCLK
Core Clock Frequency (V
DDINT
=1.14 V minimum) 1.20 V 600
2
MHz
f
CCLK
Core Clock Frequency (V
DDINT
=1.093 V minimum) 1.15 V 533
3
MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 1.045 V minimum)
4
1.10 V 400 MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 0.95 V minimum) 1.0 V 400 MHz
1
See the Ordering Guide on Page 88.
2
Applies to 600 MHz models only. See the Ordering Guide on Page 88.
3
Applies to 533 MHz and 600 MHz models only. See the Ordering Guide on Page 88.
4
Applies only to automotive products. See Automotive Products on Page 87.
Table 16. Phase-Locked Loop Operating Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
(Commercial/Industrial Models)
60 Instruction Rate
1
MHz
f
VCO
Voltage Controlled Oscillator (VCO) Frequency
(Automotive Models)
70 Instruction Rate
1
MHz
1
See the Ordering Guide on Page 88.
Table 17. SCLK Conditions for ADSP-BF523/ADSP-BF525/ADSP-BF527 Processors
V
DDEXT
/V
DDMEM
1.8 V Nominal
1
V
DDEXT
/V
DDMEM
2.5 V or 3.3 V Nominal
Parameter Max Max Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
≥ 1.14 V)
2
100 133
3
MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
< 1.14 V)
2
100 100 MHz
1
If either V
DDEXT
or V
DDMEM
are operating at 1.8 V nominal, f
SCLK
is constrained to 100 MHz.
2
f
SCLK
must be less than or equal to f
CCLK
and is subject to additional restrictions for SDRAM interface operation. See Table 38 on Page 47.
3
Rounded number. Actual test specification is SCLK period of 7.5 ns. See Table 38 on Page 47.