Datasheet

Rev. D | Page 29 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Table 11 shows settings for TWI_DT in the NONGPIO_DRIVE
register. Set this register prior to using the TWI port.
Clock Related Operating Conditions
for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Table 12 describes the core clock timing requirements for the
ADSP-BF522/ADSP-BF524/ADSP-BF526 processors. Take care
in selecting MSEL, SSEL, and CSEL ratios so as not to exceed the
maximum core clock and system clock (see Table 14). Table 13
describes phase-locked loop operating conditions.
Table 11. TWI_DT Field Selections and V
DDEXT
/V
BUSTWI
TWI_DT V
DDEXT
Nominal V
BUSTWI
Min V
BUSTWI
Nominal V
BUSTWI
Max Unit
000 (default)
1
3.3 2.97 3.3 3.63 V
001 1.8 1.7 1.8 1.98 V
010 2.5 2.97 3.3 3.63 V
011 1.8 2.97 3.3 3.63 V
100 3.3 4.5 5 5.5 V
101 1.8 2.25 2.5 2.75 V
110 2.5 2.25 2.5 2.75 V
111 (reserved)–––––
1
Designs must comply with the V
DDEXT
and V
BUSTWI
voltages specified for the default TWI_DT setting for correct JTAG boundary scan operation during reset.
Table 12. Core Clock (CCLK) Requirements (All Instruction Rates
1
) for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter Nominal Voltage Setting Max Unit
f
CCLK
Core Clock Frequency (V
DDINT
=1.33 V minimum) 1.40 V 400
2
MHz
f
CCLK
Core Clock Frequency (V
DDINT
= 1.235 V minimum) 1.30 V 300 MHz
1
See the Ordering Guide on Page 88.
2
Applies to 400 MHz models only. See the Ordering Guide on Page 88.
Table 13. Phase-Locked Loop Operating Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter Min Max Unit
f
VCO
Voltage Controlled Oscillator (VCO) Frequency 70 Instruction Rate
1
MHz
1
See the Ordering Guide on Page 88.
Table 14. SCLK Conditions for ADSP-BF522/ADSP-BF524/ADSP-BF526 Processors
Parameter
V
DDEXT
/V
DDMEM
1.8 V Nominal
1
V
DDEXT
/V
DDMEM
2.5 V or 3.3 V Nominal
Max Max Unit
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
≥ 1.33 V)
2
80 100 MHz
f
SCLK
CLKOUT/SCLK Frequency (V
DDINT
< 1.33 V) 80 80 MHz
1
If either V
DDEXT
or V
DDMEM
are operating at 1.8 V nominal, f
SCLK
is constrained to 80 MHz.
2
f
SCLK
must be less than or equal to f
CCLK
and is subject to additional restrictions for SDRAM interface operation. See Table 37 on Page 47.