Datasheet

Rev. D | Page 26 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Port J: Multiplexed Peripherals
PJ0: PPI_FS1/TMR0 I/O PPI Frame Sync1/Timer0 C
PJ1: PPI_CLK/TMRCLK I PPI Clock/Timer Clock
PJ2: SCL I/O 5V TWI Serial Clock (This pin is an open-drain output and requires a pull-up
resistor.
4
)
E
PJ3: SDA I/O 5V TWI Serial Data (This pin is an open-drain output and requires a pull-up
resistor.
4
)
E
Real Time Clock
RTXI I RTC Crystal Input (This ball should be pulled low when not used.)
RTXO O RTC Crystal Output (Does not three-state during hibernate.)
JTAG Port
TCK I JTAG Clock
TDO O JTAG Serial Data Out C
TDI I JTAG Serial Data In
TMS I JTAG Mode Select
TRST
I JTAG Reset (This ball should be pulled low if the JTAG port is not used.)
EMU
O Emulation Output C
Clock
CLKIN I Clock/Crystal Input
XTAL O Crystal Output (If CLKBUF is enabled, does not three-state during hibernate.)
CLKBUF O Buffered XTAL Output (If enabled, does not three-state during hibernate.) C
Mode Controls
RESET
I Reset
NMI I Nonmaskable Interrupt (This ball should be pulled high when not used.)
BMODE3–0 I Boot Mode Strap 3-0
ADSP-BF523/ADSP-BF525/ADSP-BF527 Voltage
Regulation I/F
VR
SEL
I Internal/External Voltage Regulator Select
VR
OUT
/EXT_WAKE1 O External FET Drive/Wake up Indication 1 (Does not three-state during
hibernate.)
G
EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C
SS/PG
A Soft Start/Power Good
ADSP-BF522/ADSP-BF524/ADSP-BF526 Voltage
Regulation I/F
EXT_WAKE1 O Wake up Indication 1 (Does not three-state during hibernate.) C
EXT_WAKE0 O Wake up Indication 0 (Does not three-state during hibernate.) C
PG
A Power Good (This signal should be pulled low when not used.)
Table 10. Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type
1