Datasheet

Rev. D | Page 25 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
Port G: GPIO and Multiplexed Peripherals
PG0/HWAIT I/O GPIO/Boot Host Wait
2
C
PG1/SPISS
/SPISEL1 I/O GPIO/SPI Slave Select Input/SPI Slave Select 1 C
PG2/SCK I/O GPIO/SPI Clock D
PG3/MISO/DR0SECA I/O GPIO/SPI Master In Slave Out/Sport 0 Alternate Receive Data Secondary C
PG4/MOSI/DT0SECA I/O GPIO/SPI Master Out Slave In/Sport 0 Alternate Transmit Data Secondary C
PG5/TMR1/PPI_FS2 I/O GPIO/Timer1/PPI Frame Sync2 C
PG6/DT0PRIA/TMR2/PPI_FS3 I/O GPIO/SPORT0 Alternate Primary Transmit Data / Timer2 / PPI Frame Sync3 C
PG7/TMR3/DR0PRIA/UART0TX I/O GPIO/Timer3/Sport 0 Alternate Receive Data Primary/UART0 Transmit C
PG8/TMR4/RFS0A/UART0RX/TACI4 I/O GPIO/Timer 4/Sport 0 Alternate Receive Clock/Frame Sync
/UART0 Receive/Alternate Capture Input 4
C
PG9/TMR5/RSCLK0A/TACI5 I/O GPIO/Timer5/Sport 0 Alternate Receive Clock
/Alternate Capture Input 5
D
PG10/TMR6/TSCLK0A/TACI6 I/O GPIO/Timer 6
/Sport 0 Alternate Transmit
/Alternate Capture Input 6
D
PG11/TMR7/HOST_WR
I/O GPIO/Timer7/Host DMA Write Enable C
PG12/DMAR1/UART1TXA/HOST_ACK I/O GPIO/DMA Request 1/Alternate UART1 Transmit/Host DMA Acknowledge C
PG13/DMAR0/UART1RXA/HOST_ADDR/TACI2 I/O GPIO/DMA Request 0/Alternate UART1 Receive/Host DMA Address/Alternate
Capture Input 2
C
PG14/TSCLK0A1/MDC/HOST_RD
I/O GPIO/SPORT0 Alternate 1 Transmit/Ethernet Management Channel Clock
/Host DMA Read Enable
D
PG15
3
/TFS0A/MII PHYINT/RMII MDINT/HOST_CE I/O GPIO/SPORT0 Alternate Transmit Frame Sync/Ethernet/MII PHY Interrupt/RMII
Management Channel Data Interrupt/Host DMA Chip Enable
C
Port H: GPIO and Multiplexed Peripherals
PH0/ND_D0/MIICRS/RMIICRSDV/HOST_D0 I/O GPIO/NAND D0/Ethernet MII or RMII Carrier Sense/Host DMA D0 C
PH1/ND_D1/ERxER/HOST_D1 I/O GPIO/NAND D1/Ethernet MII or RMII Receive Error/Host DMA D1 C
PH2/ND_D2/MDIO/HOST_D2 I/O GPIO/NAND D2/Ethernet Management Channel Serial Data/Host DMA D2 C
PH3/ND_D3/ETxEN/HOST_D3 I/O GPIO/NAND D3/Ethernet MII Transmit Enable/Host DMA D3 C
PH4/ND_D4/MIITxCLK/RMIIREF_CLK/HOST_D4 I/O GPIO/NAND D4/Ethernet MII or RMII Reference Clock/Host D4 C
PH5/ND_D5/ETxD0/HOST_D5 I/O GPIO/NAND D5/Ethernet MII or RMII Transmit D0/Host DMA D5 C
PH6/ND_D6/ERxD0
/HOST_D6 I/O GPIO/NAND D6/Ethernet MII or RMII Receive D0/Host DMA D6 C
PH7/ND_D7/ETxD1/HOST_D7 I/O GPIO/NAND D7/Ethernet MII or RMII Transmit D1/Host DMA D7 C
PH8/SPISEL4
/ERxD1/HOST_D8/TACLK2 I/O GPIO/Alternate Timer Clock 2/Ethernet MII or RMII Receive D1/Host DMA D8
/SPI Slave Select 4
C
PH9/SPISEL5
/ETxD2/HOST_D9/TACLK3 I/O GPIO/SPI Slave Select 5/Ethernet MII Transmit D2/Host DMA D9
/Alternate Timer Clock 3
C
PH10/ND_CE
/ERxD2/HOST_D10 I/O GPIO/NAND Chip Enable/Ethernet MII Receive D2/Host DMA D10 C
PH11/ND_WE/ETxD3/HOST_D11 I/O GPIO/NAND Write Enable/Ethernet MII Transmit D3/Host DMA D11 C
PH12/ND_RE
/ERxD3/HOST_D12 I/O GPIO/NAND Read Enable/Ethernet MII Receive D3/Host DMA D12 C
PH13/ND_BUSY/ERxCLK/HOST_D13 I/O GPIO/NAND Busy/Ethernet MII Receive Clock/Host DMA D13 C
PH14/ND_CLE/ERxDV/HOST_D14 I/O GPIO/NAND Command Latch Enable/Ethernet MII or RMII Receive Data Valid/
Host DMA D14
C
PH15/ND_ALE/COL/HOST_D15 I/O GPIO/NAND Address Latch Enable/Ethernet MII Collision/Host DMA Data 15 C
Table 10. Signal Descriptions (Continued)
Signal Name Type Function
Driver
Type
1