Datasheet

Rev. D | Page 23 of 88 | July 2013
ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527
SIGNAL DESCRIPTIONS
Signal definitions for the ADSP-BF52x processors are listed in
Table 10. In order to maintain maximum function and reduce
package size and ball count, some balls have dual, multiplexed
functions. In cases where ball function is reconfigurable, the
default state is shown in plain text, while the alternate function
is shown in italics.
All pins are three-stated during and immediately after reset,
with the exception of the external memory interface, asynchro-
nous and synchronous memory control, and the buffered XTAL
output pin (CLKBUF). On the external memory interface, the
control and address lines are driven high, with the exception of
CLKOUT, which toggles at the system clock rate. During hiber-
nate, all outputs are three-stated unless otherwise noted in
Table 10.
All I/O pins have their input buffers disabled with the exception
of the pins that need pull-ups or pull-downs, as noted in
Table 10.
It is strongly advised to use the available IBIS models to ensure
that a given board design meets overshoot/undershoot and sig-
nal integrity requirements. If no IBIS simulation is performed, it
is strongly recommended to add series resistor terminations for
all Driver Types A, C and D.
The termination resistors should be placed near the processor to
reduce transients and improve signal integrity. The resistance
value, typically 33 Ω or 47 Ω, should be chosen to match the
average board trace impedance.
Additionally, adding a parallel termination to CLKOUT may
prove useful in further enhancing signal integrity. Be sure to
verify overshoot/undershoot and signal integrity specifications
on actual hardware.
Table 10. Signal Descriptions
Signal Name Type Function
Driver
Type
1
EBIU
ADDR19–1 O Address Bus A
DATA15–0 I/O Data Bus A
ABE1–0
/SDQM1–0 O Byte Enables/Data Mask A
AMS3–0 O Asynchronous Memory Bank Selects (Require pull-ups if hibernate is used.) A
ARDY I Hardware Ready Control
AOE
O Asynchronous Output Enable A
ARE
O Asynchronous Read Enable A
AWE O Asynchronous Write Enable A
SRAS
O SDRAM Row Address Strobe A
SCAS
O SDRAM Column Address Strobe A
SWE
OSDRAM Write Enable A
SCKE O SDRAM Clock Enable (Requires a pull-down if hibernate with SDRAM self-
refresh is used.)
A
CLKOUT O SDRAM Clock Output B
SA10 O SDRAM A10 Signal A
SMS
O SDRAM Bank Select A