Datasheet

Rev. A | Page 70 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
maximum ADSCLK frequency and an ADSCLK frequency that
scales with the sampling rate with V
DD
= 3 V and V
DD
= 5 V,
respectively. In all cases, the internal reference was used.
ADC—SERIAL INTERFACE
Figure 87 (Serial Interface Timing Diagram) shows the detailed
timing diagram for serial interfacing to the ADC. The serial
clock provides the conversion clock and controls the transfer of
information from the ADC during conversion.
The CS
signal initiates the data transfer and conversion process.
The falling edge of CS
puts the track-and-hold into hold mode,
at which point the analog input is sampled and the bus is taken
out of three-state. The conversion is also initiated at this point
and requires a minimum of 14 ADSCLKs to complete. Once 13
ADSCLK falling edges have elapsed, the track-and-hold goes
back into track on the next ADSCLK rising edge, as shown in
Figure 87 (Serial Interface Timing Diagram) at Point B. If a 16
ADSCLK transfer is used, then two trailing zeros appear after
the final LSB. On the rising edge of CS
, the conversion is termi-
nated and D
OUT
A and D
OUT
B go back into three-state. If CS is
not brought high but is instead held low for a further 14 (or 16)
ADSCLK cycles on D
OUT
A, the data from Conversion B is out-
put on D
OUT
A (followed by two trailing zeros).
Likewise, if CS
is held low for a further 14 (or 16) ADSCLK
cycles on D
OUT
B, the data from Conversion A is output on
D
OUT
B.
This is illustrated in Figure 88 (Reading Data from Both ADCs
on One DOUT Line with 32 ADSCLKs) where the case for
D
OUT
A is shown. In this case, the D
OUT
line in use goes back into
three-state on the 32
nd
ADSCLK falling edge or the rising edge
of CS
, whichever occurs first.
A minimum of 14 serial clock cycles are required to perform the
conversion process and to access data from one conversion on
either data line of the ADC. CS
going low provides the leading
zero to be read in by the microcontroller or DSP. The remaining
data is then clocked out by subsequent ADSCLK falling edges,
beginning with a second leading zero. Thus, the first falling
clock edge on the serial clock has the leading zero provided and
also clocks out the second leading zero. The 12-bit result then
follows with the final bit in the data transfer valid on the 14
th
falling edge, having being clocked out on the previous (13
th
) fall-
ing edge. In applications with a slower ADSCLK, it may be
possible to read in data on each ADSCLK rising edge depending
on the ADSCLK frequency. The first rising edge of ADSCLK
after the CS
falling edge would have the second leading zero
provided, and the 13
th
rising ADSCLK edge would have DB0
provided.
Note that with fast ADSCLK values, and thus short ADSCLK
periods, in order to allow adequately for t
2
, an ADSCLK rising
edge may occur before the first ADSCLK falling edge. This ris-
ing edge of ADSCLK may be ignored for the purposes of the
timing descriptions in this section. If a falling edge of ADSCLK
is coincident with the falling edge of CS
, then this falling edge of
ADSCLK is not acknowledged by the ADC, and the next falling
edge of ADSCLK will be the first registered after the falling edge
of CS
.
Figure 85. Power vs. Throughput in Normal Mode with V
DD
= 3 V
Figure 86. Power vs. Throughput in Normal Mode with V
DD
= 5 V
THROUGHPUT (kSPS)
14000 200 400 600 800 1000 1200
POWER (mW)
10.0
9.5
9.0
8.5
8.0
7.5
7.0
6.5
6.0
5.5
5.0
24MHz ADSCLK
VARIABLE ADSCLK
T
A
= 25°C
THROUGHPUT (kSPS)
20000 200 400 600 800 1000 1200 1400 1600 1800
POWER (mW)
30
28
26
24
22
20
18
16
14
12
10
32MHz ADSCLK
VARIABLE ADSCLK
T
A
= 25°C