Datasheet

Rev. A | Page 66 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
required acquisition time for the next sampling instant at Point
B; therefore, the analog inputs are configured as differential for
that conversion.
The channels used for simultaneous conversions are selected via
the multiplexer address input pins, A0 to A2. The logic states of
these pins also need to be established prior to the acquisition
time; however, they may change during the conversion time
provided the mode is not changed. If the mode is changed from
fully differential to pseudo differential, for example, then the
acquisition time would start again from this point. The selected
input channels are decoded as shown in Table 53 (Analog Input
Type and Channel Selection).
The analog input range of the ADC can be selected as 0 V to
V
REF
or 0 V to 2 × V
REF
via the RANGE pin. This selection is
made in a similar fashion to that of the SGL/DIFF
pin by setting
the logic state of the RANGE pin a time t
acq
prior to the falling
edge of CS
. Subsequent to this, the logic level on this pin can be
altered after the third falling edge of ADSCLK. If this pin is tied
to a logic low, the analog input range selected is 0 V to V
REF
. If
this pin is tied to a logic high, the analog input range selected is
0 V to 2 × V
REF
.
Output Coding
The ADC output coding is set to either twos complement or
straight binary, depending on which analog input configuration
is selected for a conversion. Table 52 (ADC Output Coding)
shows which output coding scheme is used for each possible
analog input configuration.
Transfer Functions
The designed code transitions occur at successive integer LSB
values (1 LSB, 2 LSB, and so on). In single-ended mode, the LSB
size is V
REF
/4096 when the 0 V to V
REF
range is used, and the LSB
size is 2 × V
REF
/4096 when the 0 V to 2 × V
REF
range is used. In
differential mode, the LSB size is 2 × V
REF
/4096 when the 0 V to
V
REF
range is used, and the LSB size is 4 × V
REF
/4096 when the 0
V to 2 × V
REF
range is used. The ideal transfer characteristic for
the ADC when straight binary coding is output is shown in
Figure 78 (Straight Binary Transfer Characteristic), and the
ideal transfer characteristic for the ADC when twos comple-
ment coding is output is shown in Figure 79 (Twos
Complement Transfer Characteristic with VREF ± VREF Input
Range) (this is shown with the 2 × V
REF
range).
Figure 77. Selecting Differential or Single-Ended Configuration
ADSCLK
CS
114 141
A
SGL/DIFF
B
t
ACQ
Table 52. ADC Output Coding
SGL/DIFF RANGE Output Coding
0 (Differential Input) 0 (0 V to V
REF
) Twos complement
0 (Differential Input) 1 (0 V to 2 × V
REF
) Twos complement
1 (Single-Ended Input) 0 (0 V to V
REF
) Straight binary
1 (Single-Ended Input) 1 (0 V to2 × V
REF
) Twos complement
0 (Pseudo-Differential Input) 0 (0 V to V
REF
) Straight binary
0 (Pseudo-Differential Input) 1 (0 V to 2 × V
REF
) Twos complement
Table 53. Analog Input Type and Channel Selection
ADC A ADC B
SGL/DIFF
A2 A1 A0 V
IN+
V
IN–
V
IN+
V
IN–
Comment
1000V
A1
AGND V
B1
AGND Single ended
1001V
A2
AGND V
B2
AGND Single ended
1010V
A3
AGND V
B3
AGND Single ended
1011V
A4
AGND V
B4
AGND Single ended
1100V
A5
AGND V
B5
AGND Single ended
1101V
A6
AGND V
B6
AGND Single ended
0000V
A1
V
A2
V
B1
V
B2
Fully differential
0001V
A1
V
A2
V
B1
V
B2
Pseudo differential
0010V
A3
V
A4
V
B3
V
B4
Fully differential
0011V
A3
V
A4
V
B3
V
B4
Pseudo differential
0100V
A5
V
A6
V
B5
V
B6
Fully differential
0101V
A5
V
A6
V
B5
V
B6
Pseudo differential