Datasheet

Rev. A | Page 65 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
to make use of the full dynamic range of the part. A dc input is
applied to the V
IN–
pin. The voltage applied to this input pro-
vides an offset from ground or a pseudo ground for the V
IN+
input. The benefit of pseudo differential inputs is that they sepa-
rate the analog input signal ground from the ADC’s ground
allowing dc common-mode voltages to be cancelled.
The typical voltage range for the V
IN–
pin, while in pseudo dif-
ferential mode, is shown in Figure 74 (V
IN–
Input Voltage Range
vs. V
REF
in Pseudo Differential Mode with V
DD
= 3 V) and
Figure 75 (V
IN–
Input Voltage Range vs. V
REF
in Pseudo Differ-
ential Mode with V
DD
= 5 V). Figure 76 (Pseudo Differential
Mode Connection Diagram) shows a connection diagram for
pseudo differential mode.
Analog Input Selection
The analog inputs of the ADC can be configured as single-
ended or true differential via the SGL/DIFF
logic pin, as shown
in Figure 77 (Selecting Differential or Single-Ended Configura-
tion). If this pin is tied to a logic low, the analog input channels
to each on-chip ADC are set up as three true differential pairs. If
this pin is at logic high, the analog input channels to each on-
chip ADC are set up as six single-ended analog inputs. The
required logic level on this pin needs to be established prior to
the acquisition time and remain unchanged during the conver-
sion time until the track-and-hold has returned to track. The
track-and-hold returns to track on the 13
th
rising edge of
ADSCLK after the CS
falling edge (see Figure 87 (Serial Inter-
face Timing Diagram)). If the level on this pin is changed, it will
be recognized by the ADC; therefore, it is necessary to keep the
same logic level during acquisition and conversion to avoid cor-
rupting the conversion in progress.
For example, in Figure 77 (Selecting Differential or Single-
Ended Configuration) the SGL/DIFF
pin is set at logic high for
the duration of both the acquisition and conversion times so the
analog inputs are configured as single ended for that conversion
(Sampling Point A). The logic level of the SGL/DIFF
changed to
low after the track-and-hold returned to track and prior to the
Figure 73. Dual Op Amp Circuit to Convert a Single-Ended Bipolar Signal
into a Differential Unipolar Signal
Figure 74. V
IN-
Input Voltage Range vs. V
REF
in
Pseudo Differential Mode with V
DD
= 3 V
20k
220k
2 × V
REF
p–p
27
27
V+
V–
V+
V–
GND
2.5V
3.75V
1.25V
2.5V
3.75V
1.25V
V
IN+
ADC
1
V
IN–
440
220
0.47μF
1
ADDITIONAL PINS OMITTED FOR CLARITY.
220
220
10k
A
V
REF
(D
CAP
A/D
CAP
B)
V
REF
(V)
3.00 0.5 1.0 1.5 2.0 2.5
V
IN–
(V)
1.0
0.8
0.4
0.6
0.2
–0.2
0
–0.4
T
A
= 25°C
Figure 75. V
IN–
Input Voltage Range vs. V
REF
in
Pseudo Differential Mode with V
DD
= 5 V
Figure 76. Pseudo Differential Mode Connection Diagram
V
REF
(V)
5.00 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5
V
IN–
(V)
2.5
2.0
1.5
1.0
0.5
0
–0.5
T
A
= 25°C
DC INPUT
VOLTAGE
V
REF
p–p
V
REF (
D
CAP
A/D
CAP
B)
V
IN+
ADC
1
V
IN–
0.47μF
1
ADDITIONAL PINS OMITTED FOR CLARITY.