Datasheet

Rev. A | Page 57 of 80 | July 2011
ADSP-BF504/ADSP-BF504F/ADSP-BF506F
ADC—TIMING SPECIFICATIONS
ADC—ABSOLUTE MAXIMUM RATINGS
Stresses above those listed in Table 51 may cause permanent
damage to the device. This is a stress rating only; functional
operation of the device at these or any other conditions above
those indicated in the operational section of this specification is
not implied. Exposure to absolute maximum rating conditions
for extended periods may affect device reliability.
Table 50. Serial Data Interface
1
1
See Figure 87 on Page 71 and Figure 88 on Page 71.
Parameter Specification Unit Test Conditions / Comments
f
ADSCLK
2
2
Minimum ADSCLK for specified performance; with slower ADSCLK frequencies, performance specifications apply typically.
1/32 MHz min/max
t
CONVERT
14 × t
ADSCLK
ns max t
ADSCLK
= 1/f
ADSCLK
437.5 ns max f
ADSCLK
= 32 MHz, f
SAMPLE
= 2 MSPS; AV
DD
, DV
DD
= 5 V
560.0 ns max f
ADSCLK
= 25 MHz, f
SAMPLE
= 1.56 MSPS; AV
DD
, DV
DD
= 3 V
583.3 ns max f
ADSCLK
= 24 MHz, f
SAMPLE
= 1.5 MSPS; AV
DD
, DV
DD
= 2.7 V
t
QUIET
30 ns min Minimum time between end of serial read and next falling edge of CS
t
2
18/23 ns min CS to ADSCLK setup time; V
DD
= 5 V/3 V
t
3
15 ns max Delay from CS until D
OUT
A and D
OUT
B are three-state disabled
t
4
3
3
The time required for the output to cross 0.4 V or 2.4 V.
27/36 ns max Data access time after ADSCLK falling edge, V
DD
= 5 V/3 V
t
5
0.45 t
ADSCLK
ns min ADSCLK low pulse width
t
6
0.45 t
ADSCLK
ns min ADSCLK high pulse width
t
7
5/10 ns min ADSCLK to data valid hold time, V
DD
= 5 V/3 V
t
8
15 ns max CS rising edge to D
OUT
A, D
OUT
B, high impedance
t
9
30 ns min CS rising edge to falling edge pulse width
t
10
5/35 ns min/max ADSCLK falling edge to D
OUT
A, D
OUT
B, high impedance
Table 51. Absolute Maximum Ratings
Parameter Rating
AV
DD
, DV
DD
to AGND –0.3 V to +7 V
DV
DD
to DGND –0.3 V to +7 V
V
DRIVE
to DGND –0.3 V to DV
DD
V
DRIVE
to AGND –0.3 V to AV
DD
AV
DD
to DV
DD
–0.3 V to +0.3 V
AGND to DGND –0.3 V to +0.3 V
Analog Input Voltage to AGND –0.3 V to AV
DD
+ 0.3 V
Digital Input Voltage to DGND –0.3 V to +7 V
Digital Output Voltage to GND –0.3 V to V
DRIVE
+ 0.3 V
V
REF
to AGND –0.3 V to AV
DD
+ 0.3 V
Input Current to Any ADC Pin
Except Supplies
1
1
Transient currents of up to 100 mA will not cause latch up.
±10 mA
Storage Temperature Range See Table 20 on Page 30
Junction Temperature Under Bias See Table 20 on Page 30